AD824
(@ V = 5.0 V, VCM = 0 V, TA = 25ꢁC unless otherwise noted)
WAFER TEST LIMITS
S
Parameter
Symbol
Conditions
Limit
Unit
Offset Voltage
Input Bias Current
VOS
IB
1.0
12
mV max
pA max
Input Offset Current
IOS
20
pA
Input Voltage Range
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
–0.2 to 3.0
66
70
15
4.975
25
600
V min
dB min
mV/V
V/mV min
V min
mV max
mA max
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
VCM = 0 V to 2 V
V = + 2.7 V to +12 V
RL = 2 kW
ISOURCE = 20 mA
ISINK = 20 mA
Supply Current/Amplifier
VO = 0 V, RL = •
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS1
V
CC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –VS – 0.2 V to +VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
AD824A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Junction Temperature Range
R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C
I5
I6
Q18
Q29
R1
J1
R2
R9
Q21 Q27
Q4
Q6
C3
Q5
J2
Q20
Q23
Q19
Q22
+IN
R7
Q7
C2
C4
R13
–IN
R15
V
OUT
2
Q24 Q25
Package Type
qJA
qJC
Unit
Q8
C1
14-Lead SOIC (R)
16-Lead SOIC (R)
120
92
36
27
∞C/W
∞C/W
Q2
Q3
Q31
Q28
NOTES
Q26
R12
I1
R14
I2
R17
1 Absolute maximum ratings apply to packaged parts unless otherwise noted.
2 qJA is specified for the worst case conditions, i.e., qJA is specified for device in socket
for P-DIP packages; qJA is specified for device soldered in circuit board for SOIC
package.
I3
V
I4
EE
Figure 1. Simplified Schematic of 1/4 AD824
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD824AR-14
AD824AR-14-3V –40∞C to +85∞C 14-Pin SOIC
AD824AR-16
–40∞C to +85∞C 14-Pin SOIC
R-14
R-14
R-16
–40∞C to +85∞C 16-Pin SOIC
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–5–
ADI [ ADI ]
