AD8244
LOW NOISE, JFET INPUT BUFFER
The voltage noise of the
can be reduced by placing
multiple buffers in parallel. For example, two buffers in parallel
reduce the voltage noise by √2, or all four buffers placed in
parallel act as a buffer with ½ the noise. The trade-offs to this
method are increased bias current, current noise, and input
capacitance. Place a small resistor, such as 50 Ω, between the
outputs to avoid extra current flow due to the slight differences
between each output. For less power sensitive applications, these
50 Ω resistors can be omitted to boost the available output current.
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Data Sheet
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Figure 47. Reducing the Voltage Noise
Rev. 0 | Page 18 of 20
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