AD822
2µs
1V
1V
2µs
100
90
100
90
10
0%
GND
1V
1V
10
0%
GND
a
1V
10µs
100
90
+V
S
Figure 37. VS = +5 V, 0 V; Gain of Two Inverter Response
to 2.5 V Step Centered –1.25 V Below Ground, RL = 10 kΩ
10
GND
0%
1V
500mV
10µs
b.
+5V
100
90
R
P
V
IN
V
OUT
10
0%
GND
Figure 39. (a) Response with RP = 0; VIN from 0 to +VS
(b) VIN = 0 to +VS + 200 m V
VOUT = 0 to +VS
RP = 49.9 kΩ
Figure 38. VS = 3 V, 0 V; Gain of Two Inverter, VIN = 1.25 V,
25 kHz, Sine Wave Centered at –0.75 V, RL = 600 Ω
Since the input stage uses n-channel JFET s, input current
during normal operation is negative; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS – 0.4 V, the input current will reverse direction as
internal device junctions become forward biased. T his is
illustrated in Figure 4.
AP P LICATIO N NO TES
INP UT CH ARACTERISTICS
In the AD822, n-channel JFET s are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –VS to 1 V
less than +VS. Driving the input voltage closer to the positive
rail will cause a loss of amplifier bandwidth (as can be seen by
comparing the large signal responses shown in Figures 31 and
34) and increased common-mode voltage error as illustrated in
Figure 17.
A current limiting resistor should be used in series with the
input of the AD822 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage will be applied to the AD822 when ±VS = 0. T he
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up
to 10 volts of continuous overvoltage, and increases the input
voltage noise by a negligible amount.
T he AD822 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 39a shows the response of an
AD822 voltage follower to a 0 V to +5 V (+VS) square wave
input. T he input and output arc superimposed. T he output
tracks the input up to +VS without phase reversal. T he reduced
bandwidth above a 4 V input causes the rounding of the output
wave form. For input voltages greater than +VS, a resistor in
series with the AD822’s noninverting input will prevent phase
reversal, at the expense of greater input voltage noise. T his is
illustrated in Figure 39b.
Input voltages less than –VS are a completely different story.
T he amplifier can safely withstand input voltages 20 volts below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 volts. In
addition, the input stage typically maintains picoamp level input
currents across that input voltage range.
REV. A
–13–
ADI [ ADI ]
