AD817
+VS
D RIVING CAP ACITIVE LO AD S
T he internal compensation of the AD817, together with its high
output current drive, permit excellent large signal performance
while driving extremely high capacitive loads.
1kΩ
OUTPUT
3.3µF
CF
+VS
–IN
+IN
0.01µF
RIN
1kΩ
HP
PULSE
GENERATOR
VIN
7
AD817
4
TEKTRONIX
7A24
PREAMP
TEKTRONIX
P6201 FET
PROBE
2
3
VOUT
6
50Ω
0.01µF
3.3µF
CL
1000pF
–VS
NULL 1
NULL 8
–VS
Figure 31. Sim plified Schem atic
INP UT CO NSID ERATIO NS
Figure 30a. Inverting Am plifier Driving a 1000 pF
Capacitive Load
An input protection resistor (RIN in Figure 22) is required in cir-
cuits where the input to the AD817 will be subjected to tran-
sient or continuous overload voltages exceeding the +6 V
maximum differential limit. T his resistor provides protection for
the input transistors by limiting their maximum base current.
5V
500ns
100
90
100pF
For high performance circuits, it is recommended that a “bal-
ancing” resistor be used to reduce the offset errors caused by
bias current flowing through the input and feedback resistors.
T he balancing resistor equals the parallel combination of RIN
and RF and thus provides a matched impedance at each input
terminal. T he offset voltage error will then be reduced by more
than an order of magnitude.
10
1000pF
0%
5V
GRO UND ING & BYP ASSING
When designing high frequency circuits, some special precau-
tions are in order. Circuits must be built with short interconnect
leads. When wiring components, care should be taken to pro-
vide a low resistance, low inductance path to ground. Sockets
should be avoided, since their increased interlead capacitance
can degrade circuit bandwidth.
Figure 30b. Inverting Am plifier Pulse Response While
Driving Capacitive Loads
TH EO RY O F O P ERATIO N
T he AD817 is a low cost, wide band, high performance opera-
tional amplifier which effectively drives heavy capacitive or resis-
tive loads. It also provides a constant slew rate, bandwidth and
settling time over its entire specified temperature range.
Feedback resistors should be of low enough value (<1 kΩ) to
assure that the time constant formed with the inherent stray
capacitance at the amplifier’s summing junction will not limit
performance. T his parasitic capacitance, along with the parallel
resistance of RF/RIN, form a pole in the loop transmission which
may result in peaking. A small capacitance (1 pF–5 pF) may be
used in parallel with the feedback resistor to neutralize this effect.
T he AD817 (Figure 31) consists of a degenerated NPN differ-
ential pair driving matched PNPs in a folded-cascode gain stage.
T he output buffer stage employs emitter followers in a class AB
amplifier which delivers the necessary current to the load while
maintaining low levels of distortion.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. Ceramic disc capacitors of 0.1 µF
are recommended.
T he capacitor, CF, in the output stage mitigates the effect of
capacitive loads. At low frequencies, and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case, CF is bootstrapped and does not
contribute to the overall compensation capacitance of the device.
As the capacitive load is increased, a pole is formed with the
output impedance of the output stage. T his reduces the gain,
and therefore, CF is incompletely bootstrapped. Effectively,
some fraction of CF contributes to the overall compensation
capacitance, reducing the unity gain bandwidth. As the load
capacitance is further increased, the bandwidth continues to fall,
maintaining the stability of the amplifier.
+VS
2
3
7
6
AD817
8
1
4
10kΩ
VOS ADJUST
–VS
Figure 32. Offset Null Configuration
REV. B
–9–
ADI [ ADI ]
