AD8138
The Impact of Mismatches in the Feedback Networks
As mentioned previously, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop will still force the outputs to remain balanced. The ampli-
tudes of the signals at each output will remain equal and 180
degrees out of phase. The input-to-output differential-mode
gain will vary proportionately to the feedback mismatch, but the
output balance will be unaffected.
Setting the Output Common-Mode Voltage
The AD8138’s VOCM pin is internally biased at a voltage ap-
proximately equal to the midsupply point (average value of the
voltages on V+ and V–). Relying on this internal bias will result
in an output common-mode voltage that is within about 100 mV
of the expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
The output common-mode offset specified on pages 2 and 3
assume the VOCM input is driven by a low impedance voltage
source.
Ratio matching errors in the external resistors will result in a
degradation of the circuit’s ability to reject input common-mode
signals, much the same as for a four-resistor difference amplifier
made from a conventional op amp.
Also, if the dc levels of the input and output common-mode
voltages are different, matching errors will result in a small
differential-mode output offset voltage. For G = 1 case, with a
ground referenced input signal and the output common-mode
level set for 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% toler-
ance resistors are used. Resistors of 1% tolerance will result in a
worst case input CMRR of about 40 dB, worst case differential
mode output offset of 25 mV due to 2.5 V level-shift, and no
significant degradation in output balance error.
Driving a Capacitive Load
A purely capacitive load can react with the pin and bondwire
inductance of the AD8138 resulting in high frequency ringing in
the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance should be small to avoid destabilizing the amplifier.
An alternative technique is to place a small resistor in series with
the amplifier’s outputs as shown in Figure 24.
LAYOUT, GROUNDING AND BYPASSING
As a high speed part, the AD8138 is sensitive to the PCB envi-
ronment in which it has to operate. Realizing its superior specifi-
cations requires attention to various details of good high speed
PCB design.
Calculating an Application Circuit’s Input Impedance
The effective input impedance of a circuit such as that in Figure
36, at +DIN and –DIN, will depend on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the input impedance (RIN,dm)
between the inputs (+DIN and –DIN) is simply:
The first requirement is for a good solid ground plane that cov-
ers as much of the board area around the AD8138 as possible.
The only exception to this is that the two input pins (Pins 1 and
8) should be kept a few mm from the ground plane, and ground
should be removed from inner layers and the opposite side of
the board under the input pins. This will minimize the stray
capacitance on these nodes and help preserve the gain flatness
vs. frequency.
R
IN,dm = 2 × RG
In the case of a single-ended input signal, (for example if –DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes:
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 µF to 0.1 µF for each
supply. Further away, low frequency bypassing should be pro-
vided with 10 µF tantalum capacitors from each supply to
ground.
RG
RF
RIN,dm
=
1 −
2 × RG + RF
(
)
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
The signal routing should be short and direct in order to avoid
parasitic effects. Wherever there are complementary signals, a
symmetrical layout should be provided to the extent possible to
maximize the balance performance. When running differential
signals over a long distance, the traces on PCB should be close
together or any differential wiring should be twisted together to
minimize the area of the loop that is formed. This will reduce
the radiated energy and make the circuit less susceptible to
interference.
Input Common-Mode Voltage Range in Single Supply
Applications
The AD8138 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input this would imply, for
example, that the voltage at –DIN in Figure 1 would be zero
volts when the amplifier’s negative power supply voltage (at V–)
was also set to zero volts.
–10–
REV. A
ADI [ ADI ]
