AD8110/AD8111
PIN FUNCTION DESCRIPTIONS
Pin Name
INxx
DATA IN
CLK
DATA OUT
UPDATE
RESET
CE
SER/PAR
OUTyy
AGND
DVCC
DGND
AVEE
AVCC
AGNDxx
AVCCxx/yy
AVEExx/yy
A0
A1
A2
D0
D1
D2
D3
D4
Pin Numbers
66, 68, 70, 72, 74, 76, 78,
1, 3, 5, 7, 9, 11, 13, 15, 64
57
58
59
56
61
60
55
41, 38, 35, 32, 29, 26, 23, 20
2, 4, 6, 8, 10, 12, 14, 16, 46
65, 67, 69, 71, 73, 75, 77
63, 79
62, 80
17, 45
18, 44
42, 39, 36, 33, 30, 27, 24, 21
43, 37, 31, 25, 22, 19
40, 34, 28, 22
54
53
52
51
50
49
48
47
Pin Description
Analog Inputs; xx = Channel Numbers 00 Through 15.
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling Edge Triggered.
Serial Data Out, TTL Compatible.
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “High.”
Disable Outputs, Active “Low.”
Chip Enable, Enable “Low.”
Must be “low” to clock in and latch data.
Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.”
Must be connected.
Analog Outputs yy = Channel Numbers 00 Through 07.
Analog Ground for Inputs and Switch Matrix.
5 V for Digital Circuitry.
Ground for Digital Circuitry.
–5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
Ground for Output Amp, xx = Output Channel Numbers 00 Through 07.
Must be connected.
+5 V for Output Amplifier that is shared by Channel Numbers xx and yy.
Must be connected.
–5 V for Output Amplifier that is shared by Channel Numbers xx and yy.
Must be connected.
Parallel Data Input, TTL Compatible (Output Select LSB).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select MSB).
Parallel Data Input, TTL Compatible (Input Select LSB).
Parallel Data Input, TTL Compatible (Input Select).
Parallel Data Input, TTL Compatible (Input Select).
Parallel Data Input, TTL Compatible (Input Select MSB).
Parallel Data Input, TTL Compatible (Output Enable).
V
CC
ESD
INPUT
ESD
V
CC
ESD
OUTPUT
ESD
AV
EE
1k
(AD8111 ONLY)
RESET
V
CC
ESD
20k
ESD
AV
EE
DGND
a. Analog Input
V
CC
ESD
INPUT
ESD
b. Analog Output
V
CC
2k
ESD
c.
Reset
Input
OUTPUT
ESD
DGND
DGND
d. Logic Input
Figure 5. I/O Schematics
e. Logic Output
REV. A
–7–
AD [ ANALOG DEVICES ]
