AD807
30
TEST CONDITIONS
WORST CASE:
– 40°C, 4.5V
25
20
15
10
XFCB’s dielectric isolation allows the different blocks within
this mixed-signal IC to be isolated from each other, hence the
2 mV Sensitivity is achieved. Traditionally, high speed compara-
tors are plagued by crosstalk between outputs and inputs, often
resulting in oscillations when the input signal approaches 10 mV.
The AD807 quantizer toggles at
±
650
µV
(1.3 mV sensitivity) at
the input without making bit errors. When the input signal is
lowered below
±
650
µV,
circuit performance is dominated by
input noise, and not crosstalk.
0.1µF
PIN 13
500Ω
0.1µF 500Ω
QUANTIZER
INPUT
OPTIONAL FILTER
FERRITE BEAD
0.1µF
PERCENTAGE – %
5
0
1.4
1.5
1.6
1.7
1.8
1.9
2.0
RMS JITTER – Degrees
2.1
2.2
2.3
NIN 12
50Ω
50Ω
3.65kΩ
AV
CC2
14
0.1µF
AV
CC1
11
0.1µF
+5V
309Ω
0.1µF
0.1µF
50Ω
311MHz
NOISE
INPUT
AD807
Figure 12. Output Jitter Histogram
1E+3
CHOKE
"BIAS TEE"
10µF
JITTER TOLERANCE – UI
100E+0
V
CC1
V
CC2
6
0.1µF
3
0.1µF
10E+0
AD807
1E+0
Figure 15. Power Supply Noise Sensitivity Test Circuit
0.1µF
PIN 13
SONET MASK
100E–3
10E+0
500Ω
0.1µF 500Ω
NIN 12
1E+6
10E+6
QUANTIZER
INPUT
100E+0
10E+3
100E+3
1E+3
FREQUENCY – Hz
50Ω
50Ω
3.65kΩ
309Ω
CHOKE
"BIAS TEE"
0.1µF
50Ω
311MHz
NOISE
INPUT
AD807
Figure 13. Jitter Tolerance
AV
CC2
14
0.1µF
0.1µF
AV
CC1
11
0.1µF
V
CC1
V
CC2
6
0.1µF
3
0.1µF
3.0
+5V
10µF
PSR – NO FILTER
JITTER – ns p-p
2.0
CMR
1.0
Figure 16. Common-Mode Rejection Test Circuit
Signal Detect
PSR – WITH FILTER
0
0
0.1
0.2
0.4
0.6
0.3
0.5
0.7
NOISE – Vp-p @311MHz
0.8
0.9
1.0
Figure 14. Output Jitter vs. Supply Noise and
Output Jitter vs. Common Mode Noise
THEORY OF OPERATION
Quantizer
The quantizer (comparator) has three gain stages, providing a
net gain of 350. The quantizer takes full advantage of the Extra
Fast Complementary Bipolar (XFCB) process. The input stage
uses a folded cascode architecture to virtually eliminate pulse
width distortion, and to handle input signals with common-
mode voltage as high as the positive supply. The input offset
voltage is factory trimmed and guaranteed to be less than 500
µV.
REV. A
–7–
The input to the signal detect circuit is taken from the first stage
of the quantizer. The input signal is first processed through a
gain stage. The output from the gain stage is fed to both a posi-
tive and a negative peak detector. The threshold value is sub-
tracted from the positive peak signal and added to the negative
peak signal. The positive and negative peak signals are then
compared. If the positive peak, POS, is more positive than the
negative peak, NEG, the signal amplitude is greater than the
threshold, and the output, SDOUT, will indicate the presence
of signal by remaining low. When POS becomes more negative
than NEG, the signal amplitude has fallen below the threshold,
and SDOUT will indicate a loss of signal (LOS) by going high.
The circuit provides hysteresis by adjusting the threshold level
higher by a factor of two when the low signal level is detected.
This means that the input data amplitude needs to reach twice
the set LOS threshold before SDOUT will signal that the data is
again valid. This corresponds to a 3 dB optical hysteresis.
AD [ ANALOG DEVICES ]
