AD8061/AD8062/AD8063
VCC
Figure 50 shows a unity-gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
2V
TO AMPLIFIER
BIAS
DISABLE
R
SERIES
V
AD8061
O
C
LOAD
VEE
V
IN
Figure 52. Disable Circuit of the AD8063
Figure 50. Series Resistor Isolating Capacitive Load
DISABLE
Figure 34 shows the AD8063 supply current vs.
voltage. Figure 35 plots the output seen when the AD8063 input
DISABLE
Voltage feedback amplifiers like those in the AD806x family are
able to drive more capacitive load without excessive peaking
when used in higher gain configurations, because the increased
noise gain reduces the bandwidth of the overall feedback loop.
Figure 51 plots the capacitance that produces 30% overshoot vs.
noise gain for a typical amplifier.
is driven with a 10 MHz sine wave, and the
is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off
time. Figure 33 shows the input/output isolation response with
the AD8063 shut off.
10k
BOARD LAYOUT CONSIDERATIONS
Maintaining the high speed performance of the AD806x family
requires the use of high speed board layout techniques and low
parasitic components.
R
= 4.7
S
1k
100
10
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. Remove the ground plane near the package to reduce
parasitic capacitance.
R
= 0
S
Proper bypassing is critical. Use a ceramic 0.1 μF chip capacitor
to bypass both supplies. Locate the chip capacitor within 3 mm
of each power pin. Additionally, connect in parallel a 4.7 μF to
10 μF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.
1
2
3
4
5
CLOSED-LOOP GAIN
Figure 51. Capacitive Load vs. Closed-Loop Gain
Minimizing parasitic capacitance at the amplifier’s inverting
input pin is very important. Locate the feedback resistor close to
the inverting input pin. The value of the feedback resistor may
come into play—for instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown
DISABLE
in Figure 52. When the
node is pulled below 2 V
from the positive supply, the supply current decreases from
typically 6.5 mA to under 400 μA, and the AD8063 output
will enter a high impedance state. If the
connected and allowed to float, the AD8063 stays biased at
full power.
DISABLE
node is not
Rev. D | Page 16 of 20
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