AD8055/AD8056
5
4
POWER DISSIPATION LIMITS
402Ω
402Ω
With a 10 V supply (total VCC − VEE), the quiescent power
dissipation of the AD8055 in the SOT-23-5 package is 65 mW,
while the quiescent power dissipation of the AD8056 in the
MSOP-8 is 120 mW. This translates into a 15.6°C rise above the
ambient for the SOT-23-5 package and a 24°C rise for the
MSOP-8 package.
3
C
= 30pF
L
C
100Ω
V
= 0dBm
L
IN
2
50Ω
1
0
C
L
= 20pF
= 10pF
–1
–2
–3
–4
–5
C
L
The power dissipated under heavy load conditions is
approximately equal to the supply voltage minus the output
voltage, times the load current, plus the quiescent power
previously computed. The total power dissipation is then
multiplied by the thermal resistance of the package to find the
temperature rise, above ambient, of the part. The junction
temperature should be kept below 150°C.
C
= 0pF
L
0.3
1
10
FREQUENCY (MHz)
100
500
Figure 39. Capacitive Load Drive
In general, to minimize peaking or to ensure the stability for
larger values of capacitive loads, a small series resistor, RS, can
be added between the op amp output and the capacitor, CL. For
the setup depicted in Figure 40, the relationship between RS and
CL was empirically derived and is shown in Figure 41. RS was
chosen to produce less than 1 dB of peaking in the frequency
response. Note also that after a sharp rise, RS quickly settles to
approximately 25 ꢀ.
The AD8055 in the SOT-23-5 package can dissipate 270 mW,
while the AD8056 in the MSOP-8 package can dissipate
325 mW (at 85°C ambient) without exceeding the maximum
die temperature. In the case of the AD8056, this is greater than
1.5 V rms into 50 ꢀ, enough to accommodate a 4 V p-p sine
wave signal on both outputs simultaneously. However, because
each output of the AD8055 or AD8056 is capable of supplying
as much as 110 mA into a short circuit, a continuous short-
circuit condition will exceed the maximum safe junction
temperature.
402Ω
+5V
0.1µF
6
10µF
RESISTOR SELECTION
402Ω
7
2
3
FET PROBE
Table 3 is a guide for resistor selection for maintaining gain
flatness vs. frequency for various values of gain.
R
S
V
AD8055
OUT
C
L
4
V
= 0dBm
IN
Table 3.
Gain
+1
+2
+5
+10
50Ω
0.1µF
10µF
RF (Ω)
0
402
1 k
RG (Ω)
−3 dB Bandwidth (MHz)
–5V
300
160
45
Figure 40. Setup for RS vs. CL
402
249
100
40
35
30
25
20
15
10
5
909
20
DRIVING CAPACITIVE LOADS
When driving a capacitive load, most op amps exhibit peaking
in the frequency response just before the frequency rolls off.
Figure 39 shows the responses for an AD8056 running at a gain
of +2, with an 100 ꢀ load that is shunted by various values of
capacitance. It can be seen that under these conditions the part
is still stable with capacitive loads of up to 30 pF.
0
0
10
20
30
40
(pF)
50
60
270
C
L
Figure 41. RS vs. CL
Rev. J | Page 13 of 16
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