AD8051/AD8052/AD8054
problems caused by junction isolation. These features allow the
construction of high frequency, low distortion amplifiers with low
supply currents. This design uses a differential output input stage
to maximize bandwidth and headroom (see Figure 1). The smaller
signal swings required on the first stage outputs (nodes S1P, S1N)
reduce the effect of nonlinear currents due to junction capacitances
and improve the distortion performance. With this design har-
monic distortion of –80 dBc @ 1 MHz into 100
Ω
with V
OUT
=
2 V p-p (Gain = +1) on a single 5 V supply is achieved.
The inputs of the device can handle voltages from –0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values will not cause phase reversal; however, the input
ESD devices will begin to conduct if the input voltages exceed
the rails by greater than 0.5 V. During this overdrive condition,
the output stays at the rail.
The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common-emitter output stage.
High output drive capability is provided by injecting all out-
put stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not
shown). This circuit topology allows the AD8051/AD8052 to drive
45 mA of output current and the AD8054 to drive 30 mA of out-
put current with the outputs within 0.5 V of the supply rails.
V
CC
R26
Q4
R15 R2
V
IN
P
V
IN
N
SIP
Q2
SIN
Q11
Q24
R3
I7
Q47
I11
I8
V
CC
GAIN – dB
to a minimum. Parasitic capacitance of less than 1 pF at the
inverting input can significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 25 mm). These should be designed with a
characteristic impedance of 50
Ω
or 75
Ω
and be properly termi-
nated at each end.
Active Filters
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
Figure 42 shows an example of a 2 MHz biquad bandwidth
filter that uses three op amps of an AD8054. Such circuits are
sometimes used in medical ultrasound systems to lower the
noise bandwidth of the analog signal before A/D conversion.
Please note that the unused amplifiers’ inputs should be tied to
ground.
R6
1k
C1
50pF
R2
2k
V
IN
R1
3k
2
1
3
R3
2k
13
C2
50pF
7
5
R5
2k
9
8
10
V
OUT
14
12
R4
2k
6
I10
R39
Q5
Q25
I2
I3
Q51
Q50
Q39
Q23
I9
Q36
I5
V
EE
C3
V
OUT
C9
AD8054
AD8054
AD8054
Q40
V
EE
Q22
Q7
Q21
Q27
R23 R27
Q31
Figure 42. 2 MHz Biquad Bandpass Filter Using AD8054
The frequency response of the circuit is shown in Figure 43.
Q13
Q1
0
Q8
Q3
R5
R21
10
C7
V
EE
Figure 41. AD8051/AD8052 Simplified Schematic
APPLICATIONS
Layout Considerations
20
30
The specified high speed performance of the AD8051/AD8052/
AD8054 requires careful attention to board layout and compo-
nent selection. Proper RF design techniques and low-parasitic
component selection are necessary.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce the parasitic capacitance.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within 3 mm of each power pin. An additional large (4.7
µF
to
10
µF)
tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the parasitic capacitance at this node
REV. B
40
10k
100k
1M
FREQUENCY – Hz
10M
100M
Figure 43. Frequency Response of 2 MHz Bandpass
Biquad Filter
A/D and D/A Applications
Figure 44 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit 20 MSPS dual A/D converter. This
converter is designed to convert I and Q signals in communica-
tion systems. In this application, only the I channel is being
driven. The I channel is enabled by applying a logic HIGH to
SELECT, Pin 27.
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50
Ω
and
–13–
AD [ ANALOG DEVICES ]
