AD8051/AD8052/AD8054
reduced to −60.18 dB and the ADC operated with 8.46 ENOBs
as shown in Figure 49. The inclusion of the AD8051 in the
circuit did not worsen the distortion performance of the AD9201.
10
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG
APPLICATIONS
Figure 50 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit, 20 MSPS, dual analog-to-digital
converter. This converter is designed to convert I and Q signals in
communications systems. In this application, only the I channel
is being driven. The I channel is enabled by applying a logic
high to SELECT (Pin 13).
PART#
0
FUND
0
–10
–20
–30
–40
–50
–60
–70
–80
FFTSIZE 8192
FCLK 20.0MHz
998.5kHz
–0.51dB
–68.13
FUND
VIN
THD
SNR
54.97
SINAD 54.76
8.80
ENOB
SFDR 71.66
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and the
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22 Ω series resistor limits the maximum current
that flows and helps to lower the distortion of the ADC.
2ND
3RD
4TH
5TH
6TH
7TH
–74.53
–76.06
–76.35
–79.05
–80.36
–75.08
–88.12
–77.87
2ND
7TH
3RD
4TH
9TH
8TH
5TH
6TH
–90
–100
8TH
9TH
–110
–120
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
Figure 48. FFT Plot for AD8051 Driving the AD9201 at 1 MHz
10
0
PART#
FUND
0
The output of the op amp is ac-coupled into INA-I (Pin 16) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 kΩ resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I swings both positive
and negative with respect to the bias voltage applied to INB-I.
FFTSIZE 8192
FCLK 20.0MHz
FUND 9.5MHz
–10
–20
–30
–40
–50
VIN
–0.44dB
–57.08
54.65
THD
SNR
SINAD 52.69
ENOB 8.46
2ND
3RD
60.18
SFDR
2ND
3RD
4TH
5TH
6TH
With the sampling clock running at 20 MSPS, the analog-to-
digital output was analyzed with a digital analyzer. Two input
frequencies were used, 1 MHz and 9.5 MHz, which is just short
of the Nyquist frequency. These signals were well filtered to
minimize any harmonics.
–60
–70
–80
–60.18
–60.23
–82.01
–78.83
–81.28
–77.28
–84.54
7TH
5TH
4TH
8TH
6TH
–90
–100
7TH
8TH
9TH
–110
–120
–92.78
Figure 48 shows the FFT response of the ADC for the case of a
1 MHz analog input. The SFDR is 71.66 dB, and the analog-to-
digital is producing 8.8 ENOB (effective number of bits). When
the analog frequency was raised to 9.5 MHz, the SFDR was
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
Figure 49. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz
14
13
CLOCK
15
16
SLEEP
INA-I
0.33µF
22Ω
+V
SELECT
DD
+5V
10pF
1kΩ
22Ω
INB-I
17
0.01µF
22Ω
10pF
0.1µF
6
10µF
AD9201
DATA OUT
18 REFT-I
12
11
10
9
D9
D8
D7
D6
7
3
2
0.1µF
10µF
0.1µF
19
REFB-I
50Ω
AD8051
0.1µF
20 AVSS
1kΩ
4
21
22
REFSENSE
VREF
D5
D4
8
7
6
5
4
3
2
1
10µF
0.1µF
0.1µF
10µF
–5V
23
AVDD
+5V
D3
10µF
0.1µF
1kΩ
D2
24 REFB-Q
25 REFT-Q
0.1µF
10µF
0.1µF
D1
0.1µF
D0
22Ω
DVDD
DVSS
+5V
26 INB-Q
0.1µF
10µF
10pF
22Ω
INA-Q
27
28
10pF
CHIP–SELECT
Figure 50. The AD8051 Driving an AD9201, a 10-Bit, 20 MSPS Analog-to-Digital Converter
Rev. H | Page 19 of 24
ADI [ ADI ]
