AD7904/AD7914/AD7924
TIMING SPECIFICATIONS
1
Parameter
f
SCLK2
t
CONVERT
t
QUIET
t
2
t
3 3
t
4 3
t
5
t
6
t
7
t
8 4
t
9
t
10
t
11
t
12
10
20
16
×
t
SCLK
50
10
35
40
0.4
×
t
SCLK
0.4
×
t
SCLK
10
15/45
10
5
20
1
(V
DD
= 2.7 V to 5.25 V, V
DRIVE
V
DD
, REF
IN
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Description
Limit at T
MIN
, T
MAX
AD7904/AD7914/AD7924
V
DD
= 3 V
V
DD
= 5 V
Unit
10
20
16
×
t
SCLK
50
10
30
40
0.4
×
t
SCLK
0.4
×
t
SCLK
10
15/35
10
5
20
1
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
µs
max
Minimum Quiet Time Required Between
CS
Rising Edge
and Start of Next Conversion
CS
to SCLK Setup Time
Delay from
CS
until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to DOUT Valid Hold Time
SCLK Falling Edge to DOUT High Impedance
DIN Setup Time Prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to
CS
High
Power-Up Time from Full Power-Down/Auto
Shutdown Modes
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7
×
V
DRIVE
.
4
t
8
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
–8–
REV. 0
AD [ ANALOG DEVICES ]
