AD7895
The track/hold amplifier acquires an input signal to 12-bit
accuracy in less than 0.3
µs.
The operation of the track/hold is
essentially transparent to the user. With the high sampling
operating mode, the track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion (i.e. the falling
edge of
CONVST).
The aperture time for the track/hold (i.e.
the delay time between the external
CONVST
signal and the
track/hold actually going into hold) is typically 15 ns. At the
end of conversion (on the falling edge of BUSY), the part returns
to its tracking mode. The acquisition time of the track/hold
amplifier begins at this point. For the auto shut down mode, the
rising edge of
CONVST
wakes up the part and the track, and
hold amplifier goes from its tracking mode to its hold mode 6
µs
after the rising edge of
CONVST
(provided that the
CONVST
high time is less than 6
µs).
Once again, the part returns to its
tracking mode at the end of conversion when the BUSY signal
goes low.
Reference Input
stated. If there are more serial clock pulses after the sixteenth
clock, the shift register will be moved on past its reset state.
However, the shift register will be reset again on the falling edge
of the
CONVST
signal to ensure that the part returns to a
known state every conversion cycle. As a result, a read opera-
tion from the output register should not straddle across the
falling edge of
CONVST
as the output shift register will be reset
in the middle of the read operation, and the data read back into
the microprocessor will appear invalid.
OPERATING MODES
Mode 1 Operation (High Sampling Performance)
The reference input to the AD7895 is buffered on-chip with a
maximum reference input current of 1
µA.
The part is specified
with a +2.5 V reference input voltage. Errors in the reference
source will result in gain errors in the AD7895’s transfer
function and will add to the specified full-scale errors on the
part. Suitable reference sources for the AD7895 include the
AD780 and AD680 precision +2.5 V references.
Timing and Control Section
Figure 3 shows the timing and control sequence required to
obtain optimum performance from the AD7895. In the se-
quence shown, conversion is initiated on the falling edge of
CONVST,
and new data from this conversion is available in
the output register of the AD7895 3.8
µs
later. Once the read
operation has taken place, a further 300 ns should be allowed
before the next falling edge of
CONVST
to optimize the settling
of the track/hold amplifier before the next conversion is initi-
ated. With the serial clock frequency at its maximum of
15 MHz, the achievable throughput rate for the part is 3.8
µs
(conversion time) plus 1.1
µs
(read time) plus 0.3
µs
(acquisi-
tion time). This results in a minimum throughput time of 8.2
µs
(equivalent to a throughput rate of 192 kHz). A serial clock of
less than 15 MHz can be used, but this will in turn mean that
the throughput time will increase.
The read operation consists of sixteen serial clock pulses to the
output shift register of the AD7895. After sixteen serial clock
pulses, the shift register is reset, and the SDATA line is three-
t
1
CONVST
The timing diagram in Figure 3 is for optimum performance in
operating Mode 1 where the falling edge of
CONVST
starts
conversion and puts the Track/Hold amplifier into its hold
mode. This falling edge of CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 3.8
µs
max after the falling edge of
CONVST,
and new
data from this conversion is available in the output register of
the AD7895. A read operation accesses this data. This read
operation consists of 16 clock cycles, and the length of this read
operation will depend on the serial clock frequency. For the
fastest throughput rate (with a serial clock of 15 MHz, 5 V
operation) the read operation will take 1.1
µs.
The read opera-
tion must be complete at least 300 ns before the falling edge of
the next
CONVST,
and this gives a total time of 5.2
µs
for the
full throughput time (equivalent to 192 kHz). This mode of
operation should be used for high sampling applications.
Mode 2 Operation (Auto Sleep After Conversion)
The timing diagram in Figure 4 is for optimum performance in
operating mode 2 where the part automatically goes into sleep
mode once BUSY goes low after conversion and “wakes-up”
before the next conversion takes place. This is achieved by keep-
ing
CONVST
low at the end of conversion, whereas it was high
at the end of conversion for Mode 1 Operation. The rising edge
of
CONVST
“wakes up” the part. This wake-up time is 6
µs
at
which point the Track/Hold amplifier goes into its hold mode,
provided the
CONVST
has gone low. The conversion takes
3.8
µs
after this giving a total of 9.8
µs
from the rising edge of
CONVST
to the conversion being complete, which is indi-
cated by the BUSY going low. Note that since the wake-up time
from the rising edge of
CONVST
is 6
µs,
when the
CONVST
pulse width is greater than 6
µs,
the conversion will take more
t
1
= 40ns MIN
BUSY
300ns MIN
SCLK
t
CONVERT
= 3.8µs
CONVERSION IS
INITIATED AND
TRACK/HOLD GOES INTO
HOLD
CONVERSION
ENDS
3.8µs LATER
SERIAL READ
OPERATION
READ OPERATION
SHOULD END 300ns
PRIOR TO NEXT
FALLING EDGE OF
CONVST
OUTPUT
SERIAL
SHIFT
REGISTER
IS RESET
Figure 3. Mode 1 Timing Operation Diagram for High Sampling Performance
REV. 0
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