AD7890
TIMING CHARACTERISTICS
Parameter
f
CLKIN3
t
CLK IN LO
t
CLK IN HI
tr
4
tf
4
t
CONVERT
t
CST
Self-Clocking Mode
t
1
t
2 5
t
3
t
4
t
5 5
t
6
t
7 6
t
8
t
9
t
10
t
11
t
12
External-Clocking Mode
t
13
t
145
t
15
t
16
t
175
t
18
t
196
t
19A6
t
20
t
21
t
22
t
23
1, 2
(V
DD
= +5 V
5%, AGND = DGND = 0 V, REF IN = +2.5 V, f
CLK IN
= 2.5 MHz external, MUX OUT
connected to SHA IN.)
Units
kHz min
MHz max
ns min
ns min
ns max
ns max
µs
max
ns min
ns max
ns max
ns nom
ns nom
ns max
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
Conditions/Comments
Master Clock Frequency. For Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
Digital Output Rise Time. Typically 10 ns
Digital Output Fall Time. Typically 10 ns
Conversion Time
CONVST
Pulse Width
RFS
Low to SCLK Falling Edge
RFS
Low to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Delay
SCLK Rising Edge to
RFS
Delay
Bus Relinquish Time after Rising Edge of SCLK
TFS
Low to SCLK Falling Edge
Data Valid to
TFS
Falling Edge Setup Time (A2 Address Bit)
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS
to SCLK Falling Edge Hold Time
RFS
Low to SCLK Falling Edge Setup Time
RFS
Low to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Delay
RFS
to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of
RFS
Bus Relinquish Time after Rising Edge of SCLK
TFS
Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS
to SCLK Falling Edge Hold Time
Limit at T
MIN
, T
MAX
(A, B, S Versions)
100
2.5
0.3
×
t
CLK IN
0 3
×
t
CLK IN
25
25
5.9
100
t
CLK IN HI
+ 50
25
t
CLK IN HI
t
CLK IN LO
20
40
50
0
t
CLK IN
+ 50
0
20
10
20
20
40
50
50
35
20
50
90
20
10
15
40
NOTES
1
Sample tested at –25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 8 to 11.
3
The AD7890 is production tested with f
CLK IN
at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
4
Specified using 10% and 90% points on waveform of interest.
5
These numbers are measured with the load circuit of Figure I and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus re-
linquish times of the part and as such are independent of external bus loading capacitances.
1.6mA
TO OUTPUT
PIN
50pF
200µA
+2.1V
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4–
REV. A
AD [ ANALOG DEVICES ]
