AD7824/AD7828
TIMING CHARACTERISTICS
1
(V
Parameter
t
CSS
t
CSH
t
AS
t
AH
t
RDY2
t
CRD
t
ACC13
t
ACC23
t
lNTH2
t
DH4
t
P
t
RD
Limit at 25 C
(All Grades)
0
0
0
30
40
2.0
85
50
40
75
60
500
60
600
0
0
0
35
60
2.4
110
60
65
100
70
500
80
500
DD
= 5 V; V
REF
(+) = 5 V; V
REF
(–) = GND = 0 V, unless otherwise noted.)
Limit at T
MIN
, T
MAX
(T, U Grades)
0
0
0
40
60
2.8
120
70
70
100
70
600
80
400
Unit
ns min
ns min
ns min
ns min
ns max
µs
max
ns max
ns max
ns typ
ns max
ns max
ns min
ns min
ns max
Conditions/Comments
CS
to
RD
Setup Time
CS
to
RD
Hold Time
Multiplexer Address Setup Time
Multiplexer Address Hold Time
CS
to RDY Delay. Pull-Up
Resistor 5 kΩ.
Conversion Time, Mode 0
Data Access Time after
RD
Data Access Time after
INT,
Mode 0
RD
to
INT
Delay
Data Hold Time
Delay Time between Conversions
Read Pulsewidth, Mode 1
Limit at T
MIN
, T
MAX
(K, L, B, C Grades)
NOTES
1
Sample tested at 25°C to ensure compliance. All input control signals are specified with t
RISE
= t
FALL
= 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBN
3k
DGND
100pF
DBN
3k
DGND
10pF
a. High-Z to V
OH
a. V
OH
to High-Z
5V
3k
DBN
100pF
DGND
DBN
5V
3k
10pF
DGND
b. High-Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
b. V
OL
to High-Z
Figure 2. Load Circuits for Data Hold Time Test
REV. F
–3–
AD [ ANALOG DEVICES ]
