AD7824/AD7828
MICROPROCESSOR INTERFACING
The AD7824/AD7828 is designed to interface to microprocessors
as Read Only Memory (ROM). Analog channel selection, con-
version start, and data read operations are controlled by
CS, RD,
and the channel address inputs. These signals are common to
all memory peripheral devices.
Z80 MICROPROCESSOR
to any of the addresses in Table II starts a conversion and reads
the conversion result.
MOVE
×
B $C000, D0
Once conversion has begun, the MC68000 inserts WAIT states
until INT goes low, asserting DTACK at the end of conversion.
The microprocessor then places the conversion results into the
D0 register.
A23
ADDRESS BUS
A1
A0
A1
Figure 16 shows a typical AD7824/AD7828–Z80 interface. The
AD7824/AD7828 is operating in Mode 0. Assume the ADC is
assigned a memory block starting at address C000. The follow-
ing LOAD instruction to any of the addresses listed in Table II
will start a conversion of the selected channel and read the
conversion result.
LD B, (C000)
At the beginning of the instruction cycle when the ADC
address is selected, RDY asserts the WAIT input so that the
Z80 is forced into a WAIT state. At the end of conversion,
RDY returns high and the conversion result is placed in the B
register of the microprocessor.
A15
ADDRESS BUS
A0
A0
A1
A2**
A1
A0
A2
A0
AS
R/W
MC68000
CLR
7474
D
5k
DTACK
D7
Q
CK
RDY
DB7
DATA BUS
D0
DB0
5V
EN
ADDRESS
DECODE
CS
RD
A1
A2**
AD7824*
AD7828*
A2
MREQ
5V
Z80
5k
WAIT
RD
D7
EN
ADDRESS
DECODE
CS
RDY
RD
DB7
DATA BUS
D0
DB0
AD7824*
AD7828*
*
LINEAR CIRCUITRY OMITTED FOR CLARITY.
**
FOR THE AD7828 ONLY
Figure 17. AD7824/AD7828–MC68000 Interface
TMS32010 MICROCOMPUTER
A TMS32010 interface is shown in Figure 18. The AD7824/
AD7828 is operating in Mode 1 (i.e., no
µP
WAIT states). The
ADC is mapped at a port address. The following I/O instruction
starts a conversion and reads the previous conversion result into
the accumulator.
IN, A PA (PA = PORT ADDRESS)
The port address (000 to 111) selects the analog channel to be
converted. When conversion is complete, a second I/O instruc-
tion (IN, A PA) reads the up-to-date data into the accumulator
and starts another conversion. A delay of 2.5
µs
must be allowed
between conversions.
PA2
PA1
PA0
TMS32010
MEN
DEN
D7
DATA BUS
D0
DB0
CS
RD
DB7
A2**
A1
A0
*
LINEAR CIRCUITRY OMITTED FOR CLARITY.
**
FOR THE AD7828 ONLY
Figure 16. AD7824/AD7828–Z80 lnterface
Table II. Address Channel Selection
Address
C000
C001
C002
C003
C004
C005
C006
C007
AD7824
Channel
1
2
3
4
AD7828
Channel
1
2
3
4
5
6
7
8
AD7824*
AD7828*
MC68000 MICROPROCESSOR
Figure 17 shows an MC68000 interface. The AD7824/AD7828
is operating in Mode 0. Assume the ADC is again assigned a
memory block starting at address C000. A MOVE instruction
*
LINEAR CIRCUITRY OMITTED FOR CLARITY.
**
FOR THE AD7828 ONLY
Figure 18. AD7824/AD7828–TMS32010 Interface
–10–
REV. F
AD [ ANALOG DEVICES ]
