a
+3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7804/AD7805/AD7808/AD7809
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Four 10-Bit DACs in One Package
Serial and Parallel Loading Facilities Available
AD7804 Quad 10-Bit Serial Loading
AD7805 Quad 10-Bit Parallel Loading
AD7808 Octal 10-Bit Serial Loading
AD7809 Octal 10-Bit Parallel Loading
+3.3 V to +5 V Operation
AV
DD
DV
DD
AGND DGND
V
F*
OUT
OUT
POWER ON
RESET
REFOUT
REFIN
1.23V REF
AD7804/
AD7808
V
E*
AV
DD
V
BIAS
DIVIDER
V
V
V
D
C
B
MUX
DAC D
OUT
OUT
OUT
COMP
CHANNEL D
CONTROL REG
DATA
REGISTER
DAC
REGISTER
Power-Down Mode
Power-On Reset
V
BIAS
MUX
DAC C
Standby Mode (All DACs/Individual DACs)
Low Power All CMOS Construction
10-Bit Resolution
Double Buffered DAC Registers
Dual External Reference Capability
DATA
REGISTER
CHANNEL C
CONTROL REG
DAC
REGISTER
V
BIAS
MUX
DAC B
CHANNEL B
CONTROL REG
DATA
REGISTER
DAC
REGISTER
APPLICATIONS
Optical Disk Drives
Instrumentation and Communication Systems
Process Control and Voltage Setpoint Control
Trim Potentiometer Replacement
Automatic Calibration
V
BIAS
V
V
A
MUX
DAC A
OUT
PD**
DATA
REGISTER
DAC
REGISTER
CHANNEL A
CONTROL REG
H*
G*
SYSTEM
CONTROL REG
OUT
V
OUT
FSIN
CLKIN
SDIN
INPUT SHIFT
REGISTER &
CONTROL LOGIC
GENERAL DESCRIPTION
The AD7804/AD7808 are quad/octal 10-bit digital-to-analog
converters, with serial load capabilities, while the AD7805/AD7809
are quad/octal 10-bit digital-to-analog converters with parallel
load capabilities. These parts operate from a +3.3 V to +5 V
(±10%) power supply and incorporates an on-chip reference.
**ONLY AD7804 SHOWN FOR CLARITY
**SHOWS ADDITIONAL CHANNELS ON THE AD7808
**PIN ON THE AD7808 ONLY
CLR LDAC
AV
DD
DV
DD
AGND DGND
V
OUT
F*
E*
POWER ON
RESET
REFOUT
REFIN
1.23V REF
AD7805/
AD7809
These DACs provide output signals in the form of VBIAS ± VSWING
VSWING is derived internally from VBIAS. On-chip control registers
include a system control register and channel control registers.
The system control register has control over all DACs in the
package. The channel control registers allow individual control
of DACs. The complete transfer function of each individual
DAC can be shifted around the VBIAS point using an on-chip
Sub DAC. All DACs contain double buffered data inputs,
which allow all analog outputs to be simultaneously updated
using the asynchronous LDAC input.
.
V
OUT
AV
DD
V
BIAS
DIVIDER
V
D
MUX
DAC D
OUT
COMP
CHANNEL D
CONTROL REG
DATA
REGISTER
DAC
REGISTER
V
BIAS
V
V
C
MUX
OUT
OUT
OUT
DAC C
DAC
REGISTER
CHANNEL C
CONTROL REG
DATA
REGISTER
V
BIAS
B
A
MUX
DAC B
Control Features
Channels Controlled
Main DAC
Sub DAC
DATA
REGISTER
DAC
REGISTER
CHANNEL B
CONTROL REG
Hardware Clear
System Control
Power Down1
System Standby2
System Clear
Input Coding
Channel Control
Channel Standby2
Channel Clear
VBIAS
All
͙
͙
V
BIAS
All
All
All
All
͙
͙
͙
͙
͙
͙
V
MUX
DAC A
DATA
REGISTER
DAC
REGISTER
CHANNEL A
CONTROL REG
͙
͙
͙
PD**
SYSTEM
CONTROL REG
V
H*
G*
OUT
Selective
Selective
Selective
͙
͙
͙
INPUT
REGISTER
CS
WR
CONTROL
LOGIC
V
OUT
MODE A0 A1
DB9 DB2 DB1 DB0
A2**
CLR LDAC
NOTES
**ONLY AD7805 SHOWN FOR CLARITY
**SHOWS ADDITIONAL CHANNELS ON THE AD7809
**PIN ON THE AD7809 ONLY
1Power-down function powers down all internal circuitry including the reference.
2Standby functions power down all circuitry except for the reference.
REV. A
Index on Page 26.
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use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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Tel: 781/329-4700
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© Analog Devices, Inc., 1998
ADI [ ADI ]
