AD7804/AD7805/AD7808/AD7809
Table IVb. AD7809 DAC Data/Control Register
Selection Table
System Clear
SCLR
0
1
Normal operation.
MODE
A2
A1
A0
Function Selected
All DACs in the package are cleared to a known state
depending on the coding scheme selected. The SCLR bit
clears the Main DACs only; the Sub DACs are unaf-
fected by the system clear function. The main DAC is
cleared to different levels depending on the coding
scheme. With offset binary coding the Main DAC output
is cleared to the bottom of the transfer function VBIAS/16.
With twos complement coding the Main DAC output is
cleared to midscale VBIAS. The channel output will be the
sum of the Main DAC and Sub DAC contributions.
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAC A Control Register
DAC B Control Register
DAC C Control Register
DAC D Control Register
DAC E Control Register
DAC F Control Register
DAC G Control Register
DAC H Control Register
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAC A Data Register
DAC B Data Register
DAC C Data Register
DAC D Data Register
DAC E Data Register
DAC F Data Register
DAC G Data Register
DAC H Data Register
AD7805/AD7809 CHANNEL CONTROL REGISTER
This register allows the user to have control over individual
DACs in the package. The control bits in this register include
multiplexer output selection (MX1 and MX0), Main or Sub
DAC selection (MAIN/SUB), standby (STBY) and individual
DAC clear (CLR). The function of these bits is as follows.
Multiplexer Selection (MX1, MX0)
Table V shows the VBIAS selection using MX1 and MX0 bits in
the channel control register.
AD7805/AD7809 SYSTEM OR CHANNEL CONTROL
REGISTER SELECTION
Table V. VBIAS Selection Table
MD0
0
This enables writing to the system control register.
The contents of this are shown in Figure 12. Mode
must be low to access this control register.
MX1
MX0
VBIAS
0
0
1
1
0
1
0
1
VDD/2 (Default on Power-Up)
INTERNAL VREF
REFIN
1
This enables writing to the channel control register.
The contents of this are shown in Figure 13. Mode
must also be low to access this control register.
Undetermined
Main DAC or Sub DAC Selection
MAIN/SUB
AD7805/AD7809 SYSTEM CONTROL REGISTER
The bits in this register allow control over all DACs in the pack-
age. The control bits include data format (10/8), power down
(PD), DAC input coding select (BIN/COMP), system standby
(SSTBY) and a system clear (SCLR). The function of these bits
is as follows:
0
Writing a 0 to this bit means that the data in the next
data register write is transferred to the selected Main
DAC.
1
Writing a 1 to this bit means that the data in the next
data register write is transferred to the selected Sub DAC.
Data Format
10/8
This applies to the 10-bit parallel load feature. In byte
load mode, (Figure 15) DB0 selects the Main or Sub
DAC data registers.
0
1
10-bit parallel loading structure.
Byte loading structure. (8+2 loading).
Standby
STBY
Input Coding
BIN/COMP
0
Places the selected DAC and its associated linear cir-
cuitry in Standby Mode.
0
1
Twos complement coding.
Offset Binary Coding.
1
Normal operation (default on power-up).
Clear
CLR
Power Down
PD
0
1
Normal operation.
0
1
Complete power-down of device.
Normal operation (default on power-up).
Clears the output of the selected Main DAC to one
of two conditions depending on the input coding se-
lected. With offset binary coding the Main DAC out-
put is cleared to the bottom of the transfer function,
VBIAS/16 and with twos complement coding the Main
DAC output is cleared to midscale VBIAS. The Sub
DAC is unaffected by a clear operation. An LDAC
signal has to be applied to the DAC for a channel clear
to be implemented.
System Standby
SSTBY
0
1
Normal operation.
All DACs in the package put in standby mode (default
on power-up).
–14–
REV. A
ADI [ ADI ]
