AD7729
Table II. Receive Section Signal Ranges
Table III. Auxiliary Section Signal Ranges
Baseband Section
V
REFCAP
V
REFOUT
ADC
ADC Signal Range
V
BIAS
Differential Input
Single-Ended Input
Signal Range
Differential
Single-Ended
Signal Range
1.3 V
±
5%
1.3 V
±
10%
2 V
REFCAP
V
REFCAP
/2 to (AVDD1 – V
REFCAP
/2)
V
REFCAP
to (AVDD1 – V
REFCAP
)
V
BIAS
±
V
REFCAP
/2
V
BIAS
±
V
REFCAP
AUXDAC
Output Code
Code 000
Code 3FF
Signal Range
2/32
×
V
REFCAP
2 V
REFCAP
TIMING CHARACTERISTICS
Parameter
AUXILIARY FUNCTIONS
Clock Signals
t
1
t
2
t
3
t
4
t
5
t
6
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
Receive Section
Clock Signals
t
7
t
8
t
9
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
(AVDD1 = AVDD2 = +3 V 10%; DVDD1 = DVDD2 = +3 V
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Units
Description
10%; AGND = DGND = 0 V;
Limit at
T
A
= –40 C to +105 C
76
30.4
30.4
t
1
0.4
×
t
1
0.4
×
t
1
20
10
15
0
0
15
10
t
4
+ 15
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns min
See Figure 2.
MCLK Period
MCLK Width Low
MCLK Width High
ASCLK Period. See Figures 4 and 6.
ASCLK Width Low
ASCLK Width High
ASDI/ASDIFS Setup Before ASCLK Low
ASDI/ASDIFS Hold After ASCLK Low
ASDOFS Delay from ASCLK High
ASDOFS Hold After ASCLK High
ASDO Hold After ASCLK High
ASDO Delay from ASCLK High
ASDIFS Low to ASDI LSB Read by ASPORT
Interval Between Consecutive ASDIFS Pulses
See Figures 5 and 7.
BSCLK Period
BSCLK Width Low
BSCLK Width High
BSDI/BSDIFS Setup Before BSCLK Low
BSDI/BSDIFS HoldAfter BSCLK Low
BSDOFS Delay from BSCLK High
BSDOFS Hold After BSCLK High
BSDO Hold After BSCLK High
BSDO Delay from BSCLK High
BSDIFS Low to ASDI LSB Read by BSPORT
Interval Between Consecutive BSDIFS Pulses
t
1
0.4
×
t
1
0.4
×
t
1
20
10
15
0
0
15
10
t
7
+ 15
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns min
ASCLK = MCLK/(2
×
ASCLKRATE). ASCLKRATE can have a value from 0 . . . 1023. When ASCLKRATE = 0, ASCLK = 13 MHz.
BSCLK = MCLK/(2
×
BSCLKRATE). BSCLKRATE can have a value from 0 . . . 1023. When BSCLKRATE = 0, BSCLK = 13 MHz.
Specifications subject to change without notice.
–4–
REV. 0
AD [ ANALOG DEVICES ]
