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AD7714ARS-5 参数 Datasheet PDF下载

AD7714ARS-5图片预览
型号: AD7714ARS-5
PDF下载: 下载PDF文件 查看货源
内容描述: 3 V / 5 V , CMOS , 500微安信号调理ADC [3 V/5 V, CMOS, 500 uA Signal Conditioning ADC]
分类和应用: 转换器光电二极管
文件页数/大小: 40 页 / 308 K
品牌: ADI [ ADI ]
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AD7714  
The SYNC input can also be used as a start convert command  
allowing the AD7714 to be operated in a conventional converter  
fashion. In this mode, the rising edge of SYNC starts conversion  
and the falling edge of DRDY indicates when conversion is  
complete. The disadvantage of this scheme is that the settling  
time of the filter has to be taken into account for every data  
register update. This means that the rate at which the data regis-  
ter is updated at a three times slower rate in this mode.  
the clock source, the total current in standby mode is 400 µA  
typical with 5 V supplies and 90 µA with 3.3 V supplies. This is  
because the on-chip oscillator circuit continues to run when the  
part is in its standby mode. This is important in applications  
where the system clock is provided by the AD7714’s clock, so  
that the AD7714 produces an uninterrupted master clock even  
when it is in its standby mode.  
Accuracy  
2
Since the SYNC input (or FSYNC bit) resets the digital filter,  
the full settling-time of 3 × 1/Output Rate has to elapse before  
there is a new word loaded to the output register on the part. If  
the DRDY signal is low when SYNC returns high (or FSYNC  
goes to a 0), the DRDY signal will not be reset high by the  
SYNC (or FSYNC) command. This is because the AD7714  
recognizes that there is a word in the data register which has not  
been read. The DRDY line will stay low until an update of the  
data register takes place at which time it will go high for  
500 × tCLK IN before returning low again. A read from the data  
register resets the DRDY signal high and it will not return low  
until the settling time of the filter has elapsed (from the SYNC  
or FSYNC command) and there is a valid new word in the data  
register. If the DRDY line is high when the SYNC (or FSYNC)  
command is issued, the DRDY line will not return low until the  
settling time of the filter has elapsed.  
Sigma-Delta ADCs, like VFCs and other integrating ADCs, do  
not contain any source of nonmonotonicity and inherently offer  
no missing codes performance. The AD7714 achieves excellent  
linearity by the use of high quality, on-chip capacitors, which  
have a very low capacitance/voltage coefficient. The device also  
achieves low input drift through the use of chopper-stabilized  
techniques in its input stage. To ensure excellent performance  
over time and temperature, the AD7714 uses digital calibration  
techniques that minimize offset and gain error.  
Drift Considerations  
The AD7714 uses chopper stabilization techniques to minimize  
input offset drift. Charge injection in the analog switches and  
dc leakage currents at the sampling node are the primary  
sources of offset voltage drift in the converter. The dc input  
leakage current is essentially independent of the selected gain.  
Gain drift within the converter depends primarily upon the  
temperature tracking of the internal capacitors. It is not af-  
fected by leakage currents.  
Reset Input  
The RESET input on the AD7714 resets all the logic, the digital  
filter and the analog modulator while all on-chip registers are  
reset to their default state. DRDY is driven high and the  
AD7714 ignores all communications to any of its registers while  
the RESET input is low. When the RESET input returns high,  
the AD7714 starts to process data and DRDY will return low in  
3 × 1/Output Rate indicating a valid new word in the data regis-  
ter. However, the AD7714 operates with its default setup condi-  
tions after a RESET and it is generally necessary to set up all  
registers and carry out a calibration after a RESET command.  
Measurement errors due to offset drift or gain drift can be elimi-  
nated at any time by recalibrating the converter or by operating  
the part in the background calibration mode. Using the system  
calibration mode can also minimize offset and gain errors in the  
signal conditioning circuitry. Integral and differential linearity  
errors are not significantly affected by temperature changes.  
POWER SUPPLIES  
No specific power sequence is required for the AD7714; either  
the AVDD or the DVDD supply can come up first. While the  
latch-up performance of the AD7714 is good, it is important  
that power is applied to the AD7714 before signals at REF IN,  
AIN or the logic input pins in order to avoid latch-up. If this is  
not possible, then the current which flows in any of these pins  
should be limited. If separate supplies are used for the AD7714  
and the system digital circuitry, then the AD7714 should be  
powered up first. If it is not possible to guarantee this, then  
current limiting resistors should be placed in series with the  
logic inputs to again limit the current.  
The AD7714’s on-chip oscillator circuit continues to function  
even when the RESET input is low. The master clock signal  
continues to be available on the MCLK OUT pin. Therefore, in  
applications where the system clock is provided by the AD7714’s  
clock, the AD7714 produces an uninterrupted master clock  
during RESET commands.  
Standby Mode  
The STANDBY input on the AD7714 allows the user to place  
the part in a power-down mode when it is not required to pro-  
vide conversion results The AD7714 retains the contents of all  
its on-chip registers (including the data register) while in  
standby mode. When in standby mode, the digital interface is  
reset and DRDY is reset to a Logic 1. Data cannot be accessed  
from the part while in standby mode. When released from standby  
mode, the part starts to process data and a new word is available  
in the data register in 3 × 1/Output rate from when the STANDBY  
input goes high.  
Supply Current  
The current consumption on the AD7714 is specified for sup-  
plies in the range +3 V to +3.6 V and in the range +4.75 V to  
+5.25 V. The part operates over a +2.85 V to +5.25 V supply  
range and the IDD for the part varies as the supply voltage varies  
over this range. Figure 5 shows the variation of the typical  
IDD with VDD voltage for both a 1 MHz external clock and a  
2.4576 MHz external clock at +25°C. The AD7714 is operated  
in unbuffered mode and the internal boost bit on the part is  
turned off. The relationship shows that the IDD is minimized by  
operating the part with lower VDD voltages. IDD on the AD7714  
is also minimized by using an external master clock or by opti-  
mizing external components when using the on-chip oscillator  
circuit. The Y grade part is specified from 2.7 V to 3.3 V and  
4.75 V to 5.25 V.  
Placing the part in standby mode reduces the total current to  
5 µA typical when the part is operated from an external master  
clock, provided this master clock is stopped. If the external  
clock continues to run in standby mode, the standby current  
increases to 150 µA typical with 5 V supplies and 75 µA typical  
with 3.3 V supplies. If a crystal or ceramic resonator is used as  
REV. C  
–27–  
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