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AD7714ARS-5 参数 Datasheet PDF下载

AD7714ARS-5图片预览
型号: AD7714ARS-5
PDF下载: 下载PDF文件 查看货源
内容描述: 3 V / 5 V , CMOS , 500微安信号调理ADC [3 V/5 V, CMOS, 500 uA Signal Conditioning ADC]
分类和应用: 转换器光电二极管
文件页数/大小: 40 页 / 308 K
品牌: ADI [ ADI ]
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AD7714  
In addition, the digital filter does not provide any rejection at  
integer multiples of the digital filter’s sample frequency. How-  
ever, the input sampling on the part provides attenuation at  
multiples of the digital filter’s sampling frequency so that the  
unattenuated bands actually occur around multiples of the input  
sampling frequency fS (as defined in Table XIV). Thus, the  
unattenuated bands occur at n × fS (where n = 1, 2, 3. . .). At  
these frequencies, there are frequency bands, ±f3 dB wide (f3 dB is  
the cutoff frequency of the digital filter) at either side where  
noise passes unattenuated to the output.  
The cutoff frequency of the digital filter is determined by the  
value loaded to bits FS0 to FS11 in the Filter High and Filter  
Low Registers. Programming a different cutoff frequency via  
FS0 – FS11 does not alter the profile of the filter response; it  
changes the frequency of the notches as outlined in the Filter  
Registers section. The output update and first notch correspond  
and are determined by the relationship:  
Output Rate = fCLK IN/(N.128)  
where N is the decimal equivalent of the word loaded to the  
FS0 to FS11 bits of the Filter Registers  
Filter Characteristics  
The AD7714’s digital filter is a low-pass filter with a (sinx/x)3  
response (also called sinc3). The transfer function for this filter  
is described in the z-domain by:  
while the –3 dB frequency is determined by the relationship:  
–3 dB frequency = 0.262 × filter first notch frequency  
The filter provides a linear phase response with a group delay  
determined by:  
3
1
1 Z N  
1 Z 1  
Group Delay = –3π.(N.f/fMOD  
)
H(z) =  
×
N
where N is the decimal equivalent of the word loaded to the  
FS0 to FS11 bits of the Filter Registers and fMOD = fCLK IN/128.  
and in the frequency domain by:  
Since the AD7714 contains this on-chip, low-pass filtering, a  
settling time is associated with step function inputs and data on  
the output will be invalid after a step change until the settling  
time has elapsed. The settling time depends upon the output  
rate chosen for the filter. The settling time of the filter to a full-  
scale step input can be up to four times the output data period.  
For a synchronized step input (using the SYNC or FSYNC  
functions) the settling time is three times the output data pe-  
riod. When changing channels on the part, the change from one  
channel to the other is synchronized so the output settling time  
is also three times the output data period. Thus, in switching  
between channels, the output data register is not updated until  
the settling time of the filter has elapsed.  
1
N
Sin(N.π. f fS )3  
Sin(π. f fS )  
H( f ) =  
×
Figure 4 shows the filter frequency response for a cutoff  
frequency of 2.62 Hz which corresponds to a first filter notch  
frequency of 10 Hz. The plot is shown from dc to 65 Hz.  
This response is repeated at either side of the input sampling  
frequency and at either side of multiples of the input sampling  
frequency.  
0
–20  
–40  
Post-Filtering  
–60  
The on-chip modulator provides samples at a 19.2 kHz output  
rate with fCLK IN at 2.4576 MHz. The on-chip digital filter  
decimates these samples to provide data at an output rate that  
corresponds to the programmed output rate of the filter. Since  
the output data rate is higher than the Nyquist criterion, the  
output rate for a given bandwidth will satisfy most application  
requirements. However, there may be some applications that  
require a higher data rate for a given bandwidth and noise per-  
formance. Applications that need this higher data rate will  
require some post-filtering following the part’s digital filter.  
–80  
–100  
–120  
–140  
–160  
–180  
–200  
–220  
–240  
0
10  
20  
30  
40  
50  
60  
FREQUENCY – Hz  
For example, if the required bandwidth is 7.86 Hz but the  
required update rate is 100 Hz, the data can be taken from the  
AD7714 at the 100 Hz rate giving a –3 dB bandwidth of  
26.2 Hz. Post-filtering can be applied to this to reduce the  
bandwidth and output noise, to the 7.86 Hz bandwidth level,  
while maintaining an output rate of 100 Hz.  
Figure 4. Frequency Response of AD7714 Filter  
The response of the filter is similar to that of an averaging filter  
but with a sharper roll-off. The output rate for the digital filter  
corresponds with the positioning of the first notch of the filter’s  
frequency response. Thus, for the plot of Figure 4 where the  
output rate is 10 Hz, the first notch of the filter is at 10 Hz. The  
notches of this (sinx/x)3 filter are repeated at multiples of the  
first notch. The filter provides attenuation of better than 100 dB  
at these notches. For the example given, if the first notch is at  
10 Hz, there will be notches (and hence >100 dB rejection) at  
both 50 Hz and 60 Hz.  
Post-filtering can also be used to reduce the output noise from  
the device for bandwidths below 1.26 Hz. At a gain of 128 and  
a bandwidth of 1.26 Hz, the output rms noise is 140 nV. This  
is essentially device noise or white noise and since the input is  
chopped, the noise has a primarily flat frequency response. By  
reducing the bandwidth below 1.26 Hz, the noise in the result-  
ant passband can be reduced. A reduction in bandwidth by a  
factor of 2 results in a reduction of approximately 1.25 in the  
output rms noise. This additional filtering will result in a  
longer settling time.  
–22–  
REV. C  
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