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AD7714ARS-5 参数 Datasheet PDF下载

AD7714ARS-5图片预览
型号: AD7714ARS-5
PDF下载: 下载PDF文件 查看货源
内容描述: 3 V / 5 V , CMOS , 500微安信号调理ADC [3 V/5 V, CMOS, 500 uA Signal Conditioning ADC]
分类和应用: 转换器光电二极管
文件页数/大小: 40 页 / 308 K
品牌: ADI [ ADI ]
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AD7714  
MD2  
MD1 MD0 Operating Mode (continued)  
1
0
0
System-Offset Calibration; this activates system-offset calibration on the channel selected by CH2, CH1  
and CH0 of the Communications Register. This is a one step calibration sequence and when complete  
the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The DRDY output  
or bit goes high when calibration is initiated and returns low when this system offset calibration is com-  
plete and a new valid word is available in the data register. For this calibration type, the zero-scale cali-  
bration is performed at the selected gain on the input voltage provided at the analog input during this  
calibration sequence. This input voltage should remain stable for the duration of the calibration. The  
full-scale calibration is performed at the selected gain on an internally generated VREF/Selected Gain.  
1
0
1
Background Calibration; this activates background calibration on the channel selected by CH2, CH1  
and CH0 of the Communications Register. If the background calibration mode is on, then the AD7714  
provides continuous self-calibration of the shorted (zeroed) inputs. This calibration takes place as part  
of the conversion sequence, extending the conversion time and reducing the word rate by a factor of six.  
Its major advantage is that the user does not have to worry about recalibrating the offset of the device  
when there is a change in the ambient temperature or supplies. In this mode, the zero-scale calibration  
is performed at the selected gain on internally shorted (zeroed) inputs. The calibrations are interleaved  
with normal conversions and the calibration registers of the device are automatically updated. Because  
the background calibration does not perform full-scale calibrations, a self-calibration should be per-  
formed before placing the part in the background calibration mode.  
1
1
1
1
0
1
Zero-Scale Self-Calibration; this activates zero-scale self-calibration on the channel selected by CH2,  
CH1 and CH0 of the Communications Register. This zero-scale self-calibration is performed at the  
selected gain on internally shorted (zeroed) inputs. This is a one step calibration sequence and when  
complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The DRDY  
output or bit goes high when calibration is initiated and returns low when this zero-scale self-calibration  
is complete and a new valid word is available in the data register.  
Full-Scale Self-Calibration; this activates full-scale self-calibration on the channel selected by CH2,  
CH1 and CH0 of the Communications Register. This full-scale self-calibration is performed at the  
selected gain on an internally-generated VREF/Selected Gain. This is a one step calibration sequence and  
when complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The  
DRDY output or bit goes high when calibration is initiated and returns low when this full-scale self-  
calibration is complete and a new valid word is available in the data register.  
G2  
G1  
G0  
Gain Setting  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16  
32  
64  
128  
BO  
Burnout Current. A 0 in this bit turns off the on-chip burnout currents. This is the default (Power-On  
or RESET) status of this bit. A 1 in this bit activates the burnout currents. When active, the burnout  
currents connect to the selected analog input pair, one to the AIN(+) input and one to the AIN(–) input.  
FSYNC  
Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and  
the calibration control logic are held in a reset state and the analog modulator is also held in its reset  
state. When this bit goes low, the modulator and filter start to process data and a valid word is available  
in 3 × 1/(output update rate), i.e., the settling time of the filter. This FSYNC bit does not affect the  
digital interface and does not reset the DRDY output if it is low.  
–16–  
REV. C  
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