AD7705/AD7706
Parameter
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
Data Output Coding
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
Negative Full-Scale Calibration Limit
14
Offset Calibration Limit
14
Input Span
15
POWER REQUIREMENTS
V
DD
Voltage
Power Supply Currents
16
B Version
1
0.4
0.4
4
V
DD
–0.6
±
10
9
Binary
Offset Binary
(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
(0.8
×
V
REF
)/GAIN
(2.1
×
V
REF
)/GAIN
+2.7 to +3.3
Units
V max
V max
V min
V min
µA
max
pF typ
Conditions/Comments
I
SINK
= 800
µA
Except for MCLK OUT.
12
V
DD
= 5 V.
I
SINK
= 100
µA
Except for MCLK OUT.
12
V
DD
= 3 V.
I
SOURCE
= 200
µA
Except for MCLK OUT.
12
V
DD
= 5 V.
I
SOURCE
= 100
µA
Except for MCLK OUT.
12
V
DD
= 3 V.
Unipolar Mode
Bipolar Mode
V max
V max
V max
V min
V max
V min to V max
GAIN Is the Selected PGA Gain (1 to 128)
GAIN Is the Selected PGA Gain (1 to 128)
GAIN Is the Selected PGA Gain (1 to 128)
GAIN Is the Selected PGA Gain (1 to 128)
GAIN Is the Selected PGA Gain (1 to 128)
For Specified Performance
Digital I/Ps = 0 V or V
DD
. External MCLK IN and
CLK DIS = 1
BUF Bit = 0. f
CLKIN
= 1 MHz. Gains of 1 to 128
BUF Bit = 1. f
CLKIN
= 1 MHz. Gains of 1 to 128
BUF Bit = 0. f
CLKIN
= 2.4576 MHz. Gains of 1 to 4
BUF Bit = 0. f
CLKIN
= 2.4576 MHz. Gains of 8 to 128
BUF Bit = 1. f
CLKIN
= 2.4576 MHz. Gains of 1 to 4
BUF Bit = 1. f
CLKIN
= 2.4576 MHz. Gains of 8 to 128
For Specified Performance
Digital I/Ps = 0 V or V
DD
. External MCLK IN and
CLK DIS = 1.
BUF Bit = 0. f
CLKIN
= 1 MHz. Gains of 1 to 128
BUF Bit = 1. f
CLKIN
= 1 MHz. Gains of 1 to 128
BUF Bit = 0. f
CLKIN
= 2.4576 MHz. Gains of 1 to 4
BUF Bit = 0. f
CLKIN
= 2.4576 MHz. Gains of 8 to 128
BUF Bit = 1. f
CLKIN
= 2.4576 MHz. Gains of 1 to 4
BUF Bit = 1. f
CLKIN
= 2.4576 MHz. Gains of 8 to 128
External MCLK IN = 0 V or V
DD
. V
DD
= 5 V. See Figure 9
External MCLK IN = 0 V or V
DD
. V
DD
= 3 V
V
DD
Voltage
Power Supply Currents
16
0.32
0.6
0.4
0.6
0.7
1.1
+4.75 to +5.25
mA max
mA max
mA max
mA max
mA max
mA max
V min to V max
Standby (Power-Down) Current
17
Power Supply Rejection
18
0.45
0.7
0.6
0.85
0.9
1.3
16
8
See Note 19
mA max
mA max
mA max
mA max
mA max
mA max
µA
max
µA
max
dB typ
NOTES
1
Temperature range as follows: B Version, –40°C to +85°C.
2
These numbers are established from characterization or design at initial product release.
3
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I and III. This applies after calibration at the
temperature of interest.
4
Recalibration at any temperature will remove these drift errors.
5
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
6
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
7
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for
bipolar ranges.
8
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.
9
This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than V
DD
+ 30 mV or go more negative than
GND – 30 mV. Parts are functional with voltages down to GND – 200 mV, but with increased leakage at high temperature.
10
The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–) on the AD7705 and is given with respect to the COMMON input on the
AD7706. The absolute voltage on the analog inputs should not go more positive than V
DD
+ 30 mV, or go more negative than GND – 30 mV for specified performance, input
voltages of GND – 200 mV can be accommodated, but with increased leakage at high temperature.
11
V
REF
= REF IN(+) – REF IN(–).
12
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
13
Sample tested at +25°C to ensure compliance.
14
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s.
15
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed V
DD
+ 30 mV or go more negative than GND – 30 mV. The offset
calibration limit applies to both the unipolar zero point and the bipolar zero point.
16
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the V
DD
current and power dissipation will vary depending on the crystal or
resonator type (see Clocking and Oscillator Circuit section).
17
If the external master clock continues to run in standby mode, the standby current increases to 150
µA
typical at 5 V and 75
µA
at 3 V. When using a crystal or ceramic
resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal
or resonator type (see Standby Mode section).
18
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter
notches of 20 Hz or 60 Hz.
19
PS
RR depends on both gain and V
DD
.
Gain
V
DD
= 3 V
V
DD
= 5 V
1
86
90
2
78
78
4
85
84
8–128
93
91
Specifications subject to change without notice.
REV. A
–3–
AD [ ANALOG DEVICES ]
