欢迎访问ic37.com |
会员登录 免费注册
发布采购

AD7705BRUZ-REEL7 参数 Datasheet PDF下载

AD7705BRUZ-REEL7图片预览
型号: AD7705BRUZ-REEL7
PDF下载: 下载PDF文件 查看货源
内容描述: [3V/5V, 1 mW, 2-Channel Differential, 16-Bit Sigma-Delta ADC]
分类和应用: 光电二极管转换器
文件页数/大小: 44 页 / 470 K
品牌: ADI [ ADI ]
 浏览型号AD7705BRUZ-REEL7的Datasheet PDF文件第14页浏览型号AD7705BRUZ-REEL7的Datasheet PDF文件第15页浏览型号AD7705BRUZ-REEL7的Datasheet PDF文件第16页浏览型号AD7705BRUZ-REEL7的Datasheet PDF文件第17页浏览型号AD7705BRUZ-REEL7的Datasheet PDF文件第19页浏览型号AD7705BRUZ-REEL7的Datasheet PDF文件第20页浏览型号AD7705BRUZ-REEL7的Datasheet PDF文件第21页浏览型号AD7705BRUZ-REEL7的Datasheet PDF文件第22页  
AD7705/AD7706  
Table 16. Operating Mode Options  
MD1 MD0 Operating Mode  
0
0
0
1
Normal Mode. In this mode, the device performs normal conversions.  
Self-Calibration. This activates self-calibration on the channel selected by CH1 and CH0 of the communication register. This  
is a one-step calibration sequence. When the sequence is complete, the part returns to normal mode, with both MD1 and  
MD0 returning to 0. The DRDY output or bit goes high when calibration is initiated, and returns low when self-calibration is  
complete and a new valid word is available in the data register. The zero-scale calibration is performed at the selected gain  
on internally shorted (zeroed) inputs, and the full-scale calibration is performed at the selected gain on an internally  
generated VREF/selected gain.  
1
1
0
1
Zero-Scale System Calibration. This activates zero-scale system calibration on the channel selected by CH1 and CH0 of the  
communication register. Calibration is performed at the selected gain on the input voltage provided at the analog input  
during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The DRDY  
output or bit goes high when calibration is initiated, and returns low when zero-scale calibration is complete and a new  
valid word is available in the data register. At the end of the calibration, the part returns to normal mode, with both MD1  
and MD0 returning to 0.  
Full-Scale System Calibration. This activates full-scale system calibration on the selected input channel. Calibration is  
performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This  
input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is  
initiated, and returns low when full-scale calibration is complete and a new valid word is available in the data register. At the  
end of the calibration, the part returns to normal mode, with both MD1 and MD0 returning to 0.  
Table 17. Gain Selection  
G2  
G1  
G0  
0
1
0
1
0
1
0
1
Gain Setting  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
2
4
8
16  
32  
64  
128  
Rev. C | Page 18 of 44  
 
 复制成功!