TIMING CHARACTERISTICS
Parameter
f
CLKIN3, 4
200
5
200
5
50
50
0
50
1000
3/f
CLKIN
100
250
300
790
l/f
CLKIN
+200
(4/f
CLKIN
) +200
5
35
160
160
150
250
200
40
180
200
1, 2
(AV
DD
= DV
DD
= +5 V
10%; AV
SS
= DV
SS
= –5 V 10%; AGND = DGND = O V; f
CLKIN
=
4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV
DD
; unless otherwise noted.)
Unit
kHz min
MHz max
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns max
MHz
ns min
ns min
ns max
ns max
ns max
ns max
ns min
ns max
ns max
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
(A, B Versions)
(S, T Versions)
200
5
200
5
50
50
0
50
1000
3/f
CLKIN
100
250
300
790
l/f
CLKIN
+200
(4/f
CLKIN
) +200
5
35
160
160
150
250
200
40
180
200
Conditions/Comments
Master Clock Frequency: Internal Gate Oscillator.
Typically 4.096 MHz.
Master Clock Frequency: Externally Supplied.
Digital Output Rise Time. Typically 20 ns.
Digital Output Fall Time. Typically 20 ns.
SC1, SC2 to CAL High Setup Time.
SC1, SC2 Hold Time after CAL Goes High.
SLEEP
High to CLKIN High Setup Time.
Data Access Time (CS Low to Data Valid).
SCLK Falling Edge to Data Valid Delay (25 ns typ).
MSB Data Setup Time. Typically 380 ns.
SCLK High Pulsewidth. Typically 240 ns.
SCLK Low Pulsewidth. Typically 730 ns.
SCLK Rising Edge to Hi-Z Delay (l/f
CLKIN
+ 100 ns typ).
CS
High to Hi-Z Delay.
Serial Clock Input Frequency.
SCLK Input High Pulsewidth.
SCLK Low Pulsewidth.
Data Access Time (CS Low to Data Valid). Typically 80 ns.
SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
CS
High to Hi-Z Delay.
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
CS
Setup Time. Typically 20 ns.
Data Delay Time. Typically 90 ns.
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
t
r5
t
f5
t
1
t
2
t
36
SSC MODE
t
47
t
5
t
6
t
7
t
8
t
98
t
108, 9
SEC MODE
f
SCLK
t
11
t
12
t
137, 10
t
1411
t
158
t
168
AC MODE
t
17
t
18
t
19
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 to 6.
3
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4
The AD7701 is production tested with f
CLKIN
at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
In order to synchronize several AD7701s together using the
SLEEP
pin, this specification must be met.
7
t
4
and t
13
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8
t
9
, t
10
, t
15
, and t
16
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9
If
CS
is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10
If
CS
is activated asynchronously to
DRDY, CS
will not be recognized if it occurs when
DRDY
is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous
CS,
the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after
CS
goes low.
11
SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
–6–
REV. E
AD [ ANALOG DEVICES ]
