TIMING SPECIFICATIONS
(continued)
Parameter
Symbol
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min
Typ
Max
10
10
10
Unit
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
Refer to Figures 17 and 18 (Master Serial Interface Modes)
1
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
CNVST
LOW to SYNC Asserted Delay
(Master Serial Read after Convert)
SYNC Deasserted to BUSY LOW Delay
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
See Table II
1.25
25
5
3
5
5
25
10
10
16
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY HIGH Width Maximum
t
18
t
19
t
19
t
20
t
21
t
22
t
23
t
24
t
28
0
0
4
25
40
15
9.5
4.5
2
3
2
0
1
20
50
70
25
24
22
4
60
2.5
1
0
20
100
140
50
49
22
30
140
3.5
1
1
20
200
280
100
99
22
90
300
5.75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF*
500 A
I
OH
0.8V
2V
*IN
SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
t
DELAY
2V
0.8V
t
DELAY
2V
0.8V
Figure 1. Load Circuit for Digital Interface Timing
Figure 2. Voltage Reference Levels for Timing
–4–
REV. B
AD [ ANALOG DEVICES ]
