Preliminary Technical Data
TIMING SPECIFICATIONS
1
AD7658/AD7657/AD7656
Table 4. AV
CC
= 4.5 V to 5.5 V, V
DD
= 9.5 V to 16.5 V, V
SS
= -9.5 V to -16.5V, V
DRIVE
= 2.7V to 5.25V; T
A
= T
MIN
to T
MAX
, unless
otherwise noted
Parameter
Parallel Mode
t
CONVERT
3
t
QUIET
400
t
1
3
T
wake-up
TBD
Write Operation
t
13
0
t
14
0
t
12
20
t
15
5
t
12/14/16
5
Read Operation
t
2
0
t
3
0
t
4
0
t
5
30
t
6
30
t
7
15
25
t
9
20
Serial Interface
f
SCLK
20
t
17
10
t
18
15
t
19
20
t
20
0.4 t
SCLK
t
21
0.4 t
SCLK
t
22
5
t
23
30
Limit at T
MIN,
T
MAX
5V
Unit
µs typ
ns min
ns min
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
MHz max
ns max
ns max
ns max
ns min
ns min
ns min
ns max
Description
Conversion Time, Internal Clock
Minimum quiet time required between bus relinquish and start of next conversion
CONVST high to BUSY high
STBY rising edge to CONVST rising edge
CS to WR setup time
CS to WR Hold time
WR Pulse width
Data setup time before WR rising edge
Data hold after WR rising edge
BUSY to RD Delay
CS to RD setup time
CS to RD Hold time
RD Pulse width
Data access time after RD falling edge
Bus relinquish time after RD rising edge
Minimum time between reads
Frequency of Serial Read Clock
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK rising edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
CS rising edge to SDATA high impedance
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
03643-0-002
Figure 2. Load Circuit for Digital Output Timing Specification
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Rev. PrI | Page 9 of 25
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