AD7606/AD7606-6/AD7606-4
TIMING SPECIFICATIONS
AV
CC
= 4.75 V to 5.25 V, V
DRIVE
= 2.3 V to 5.25 V, V
REF
= 2.5 V external reference/internal reference, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
t
CYCLE
Limit at T
MIN
, T
MAX
Min
Typ
Max
Unit
Description
1/throughput rate
Parallel mode, reading during or after conversion; or serial mode: V
DRIVE
=
4.75 V to 5.25 V, reading during a conversion using D
OUT
A and D
OUT
B lines
Serial mode reading during conversion; V
DRIVE
= 3.3 V
Serial mode reading after a conversion; V
DRIVE
= 2.3 V, D
OUT
A and D
OUT
B lines
Conversion time
Oversampling off; AD7606
Oversampling off; AD7606-6
Oversampling off; AD7606-4
Oversampling by 2; AD7606
Oversampling by 4; AD7606
Oversampling by 8; AD7606
Oversampling by 16; AD7606
Oversampling by 32; AD7606
Oversampling by 64; AD7606
STBY rising edge to CONVST x rising edge; power-up time from
standby mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
Maximum delay allowed between CONVST A, CONVST B rising edges
Maximum time between last CS rising edge and BUSY falling edge
Minimum delay between RESET low to CONVST x high
5
5
9.7
t
CONV
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
3.45
4
3
2
4.15
7.87
16.05
33
66
133
257
t
WAKE-UP STANDBY
t
WAKE-UP SHUTDOWN
Internal Reference
External Reference
t
RESET
t
OS_SETUP
t
OS_HOLD
t
1
t
2
t
3
t
4
t
6
t
7
PARALLEL/BYTE READ
OPERATION
t
8
t
9
t
10
50
20
20
9.1
18.8
39
78
158
315
100
30
13
ms
ms
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
40
25
25
0
0.5
25
25
0
0
16
21
25
32
15
22
ns
ns
ns
ns
ns
ns
ns
ns
t
11
t
12
CS to RD setup time
CS to RD hold time
RD low pulse width
V
DRIVE
above 4.75 V
V
DRIVE
above 3.3 V
V
DRIVE
above 2.7 V
V
DRIVE
above 2.3 V
RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked
Rev. 0 | Page 7 of 36
AD [ ANALOG DEVICES ]
