AD7568
TIMING SPECIFICATIONS
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8 2
t
9
Limit at
T
A
= +25 C
100
40
40
30
30
5
90
70
40
DD
= +5 V
5%; I
OUT1
= I
OUT2
= 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
Description
CLKIN Cycle Time
CLKIN High Time
CLKIN Low Time
FSIN
Setup Time
Data Setup Time
Data Hold Time
FSIN
Hold Time
SDOUT Valid After CLKIN Falling Edge
LDAC, CLR
Pulse Width
Limit at
T
A
= –40 C to +85 C
100
40
40
30
30
5
90
70
40
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
8
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
t
1
CLKIN (I)
t
4
FSIN (I)
t
2
t
3
t
7
t
6
SDIN (I)
DB15
t
5
DB0
t
8
SDOUT (O)
DB15
DB0
t
9
LDAC, CLR
NOTES
1. AO IS HARDWIRED HIGH OR LOW.
Figure 1. Timing Diagram
1.6mA
I
OL
ORDERING GUIDE
TO OUTPUT
PIN
+2.1V
C
L
50pF
Model
AD7568BS
AD7568BP
Temperature
Range
–40°C to +85°C
–40°C to +85°C
Linearity
Error (LSBs)
±
0.5
±
0.5
Package
Option*
S-44
P-44A
200µA
I
OH
*S = Plastic Quad Flatpack (PQFP), P = Plastic Leaded Chip Carrier (PLCC).
Figure 2. Load Circuit for Digital Output
Timing Specifications
REV. B
–3–
AD [ ANALOG DEVICES ]
