AD744
Table IV. Performance Summary for the 3 Op Amp
Instrumentation Amplifier Circuit
Gain
1
2
10
100
RG
NC
20 kΩ
2.22 kΩ
202
Ω
Bandwidth
3.5 MHz
2.5 MHz
1 MHz
290 kHz
T Settle (0.01%)
1.5
µs
1.0
µs
2
µs
5
µs
Equation 1 would completely describe the output of the system
if not for the op amp’s finite slew rate and other nonlinear
effects. Even considering these effects, the fine scale settling to
<0.1% will be determined by the op amp’s small signal behav-
ior. Equation 1.
V
O
–
R
=
I
IN
R
(
C
L
+
C
X
)
2
G
N
s
+
+
R C
L
s
+
1
2πF
O
2πF
O
Where F
O
= the op amp’s unity gain crossover frequency
R
G
N
=
the
“noise”
gain of the circuit
1
+
R
O
This Equation May Then Be Solved for C
L
:
Equation 2.
C
L
=
2
RC
X
2πF
O
+
(
1
−
G
N
)
2
−
G
N
+
R
2πF
O
R
2πF
O
Figure 37. The Pulse Response of the 3 Op Amp
Instrumentation Amplifier. Gain = 1, l Horizontal Scale:
0.5
µ
V/div., Vertical Scale: 5 V/div. (Gain= 10)
In these equations, capacitance C
X
is the total capacitance appear-
ing at the inverting terminal of the op amp. When modeling an
I-to-V converter application, the Norton equivalent circuit of
Figure 39 can be used directly. Capacitance C
X
is the total capaci-
tance of the output of the current source plus the input capacitance
of the op amp, which includes any stray capacitance at the op
amp’s input.
C
COMP
(OPTIONAL)
AD744
R
L
R
I
O
R
O
C
X
C
L
C
LOAD
V
OUT
Figure 38. Settling Time of the 3 Op Amp Instrumentation
Amplifier. Horizontal Scale: 500 ns/div., Vertical Scale,
Pulse Input: 5 V/div., Output Settling: 1 mV/div.
Minimizing Settling Time in Real-World Applications
Figure 39. A Simplified Model of the AD744 Used as a
Current-to-Voltage Converter
An amplifier with a “single pole” or “ideal” integrator open-loop
frequency response will achieve the minimum possible settling
time for any given unity-gain bandwidth. However, when this
“ideal” amplifier is used in a practical circuit, the actual settling
time is increased above the minimum value because of added
time constants which are introduced due to additional capacitance
on the amplifier’s summing junction. The following discussion
will explain how to minimize this increase in settling time by the
selection of the proper value for feedback capacitor, C
L
.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency, f
O
, Equation 1 will accurately describe the
small signal behavior of the circuit of Figure 39. This circuit
models an op amp connected as an I-to-V converter.
When R
O
and I
O
are replaced with their Thevenin V
IN
and R
IN
equivalents, the general purpose inverting amplifier model of
Figure 40 is created. Here capacitor C
X
represents the input
capacitance of the AD744 (5.5 pF) plus any stray capacitance
due to wiring and the type of IC package employed.
C
COMP
(OPTIONAL)
AD744
R
L
R
IN
V
IN
C
X
C
L
R
V
OUT
C
LOAD
Figure 40. A Simplified Model of the AD744 Used
as an Inverting Amplifier
REV. C
–11–
AD [ ANALOG DEVICES ]
