AD7416/AD7417/AD7418
AD7416 PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
Mnemonic
SDA
SCL
OTI
Description
Digital I/O. Serial bus bidirectional data. Push-pull output.
Digital Input. Serial bus clock.
This is a logic output. The OTI is set if the result of a conversion on Channel 0 (temperature sensor) is
greater that an 8-bit word in the OTR. The signal is reset at the end of a serial read operation. Open-
drain output.
Ground reference for track-and-hold, comparator and capacitor DAC, and digital circuitry.
Digital Input. The highest programmable bit of the serial bus address.
Digital Input. The middle programmable bit of the serial bus address.
Digital Input. The lowest programmable bit of the serial bus address.
Positive Supply Voltage, 2.7 V to 5.5 V.
AD7418 PIN FUNCTION DESCRIPTION
4
5
6
7
8
GND
A2
A1
A0
V
DD
Pin No.
1
2
3
Mnemonic
SDA
SCL
OTI
Description
Digital I/O. Serial bus bidirectional data. Push-pull output.
Digital Input. Serial bus clock.
This is a logic output. The OTI is set if the result of a conversion on Channel 0 (temperature sensor) is
greater that an 8-bit word in the OTR. The signal is reset at the end of a serial read operation. Open-
drain output.
Ground reference for track-and-hold, comparator and capacitor DAC, and digital circuitry.
Analog Input Channel. The input channel is single-ended with respect to GND. The input channel can
convert voltage signals in the range 0 V to V
REF
. The analog input channel is selected by writing to the
configuration register of the AD7418 and choosing Channel 4. (See Control Byte section.)
Reference Input. An external 2.5 V reference can be connected to the AD7418 at this pin. To enable the
on-chip reference, the REF
IN
pin should be tied to GND. If an external reference is connected to the
AD7418, the internal reference will shut down.
Positive Supply Voltage, 2.7 V to 5.5 V.
Logic Input Signal. Convert start signal. The rising edge of this signal fully powers up the part. The
power-up time for the part is 4
µs.
If the
CONVST
pulse is greater than 4
µs,
the falling edge of
CONVST
places the track-and-hold mode into hold mode and initiates a conversion. If the pulse is less
than 4
µs,
an internal timer ensures that the track-and-hold does not go into hold and conversion is not
initiated until the power-up time has elapsed. The track-and-hold goes into track mode again at the end
of conversion. (See Operating Mode section.)
4
5
GND
A
IN
6
REF
IN
7
8
V
DD
CONVST
AD7416 PIN CONFIGURATION
SOIC/MSOP
AD7418 PIN CONFIGURATION
SOIC/MSOP
8
CONVST
SDA
1
SCL
2
8
V
DD
SDA
1
SCL
2
AD7416
7
A0
TOP VIEW
OTI
3
(Not to Scale)
6
A1
5
A2
AD7418
7
V
DD
TOP VIEW
OTI
3
(Not to Scale)
6
REF
IN
5
A
IN
GND
4
GND
4
REV. G
–5–
AD [ ANALOG DEVICES ]
