AD734
A PRECISION AGC LOOP
The variable denominator of the AD734 and its high gain-
bandwidth product make it an excellent choice for precise
automatic gain control (AGC) applications. Figure 13 shows a
suggested method. The input signal, E
IN
, which may have a
peak amplitude of from 10 mV to 10 V at any frequency from
100 Hz to 10 MHz, is applied to the X input, and a fixed posi-
tive voltage E
C
to the Y input. Op amp A2 and capacitor C2
form an integrator having a current summing node at its invert-
ing input. (The AD712 dual op amp is a suitable choice for this
application.) In the absence of an input, the current in D2 and
R2 causes the integrator output to ramp negative, clamped by
diode D3, which is included to reduce the time required for the
loop to establish a stable, calibrated, output level once the
circuit has received an input signal. With no input to the
denominator (U0 and U2), the gain of the AD734 is very high
(about 70 dB), and thus even a small input causes a substantial
output.
C1
1 F
A1
1 X1
E
IN
2 X2
3 U0
D3
1N914
C2
1 F
A2
NC 4 U1
5 U2
E
C
+1V TO
+10V
D2
1N914
R2
1M
R1
1M
6 Y1
7 Y2
R3
1M
AD734
VP 14
DD 13
W 12
Z1 11
Z2 10
ER 9
VN 8
–15V
0.1 F
L
L
C1
1 F
0.1 F
D1
1N914
E
OUT
+15V
The output amplitude tracks E
C
over the range +1 V to slightly
more than +10 V.
+2
+1
100kH
Z
ERROR – dB
0
–1
100H
Z
1MH
Z
–2
10m
100m
1
INPUT AMPLITUDE – Volts
10
Figure 14. AGC Amplifier Output Error vs. Input Voltage
WIDEBAND RMS-DC CONVERTER
USING U INTERFACE
The AD734 is well suited to such applications as implicit RMS-
DC conversion, where the AD734 implements the function
V
RMS
=
avg V
IN
V
RMS
[ ]
2
+15V
(13)
using its direct divide mode. Figure 15 shows the circuit.
OP AMP = AD712 DUAL
V
IN
1/2
AD708
L
U2a
AD734
1 X1
2 X2
3 U0
4 U1
5 U2
6 Y1
L
7 Y2
VP 14
DD 13
W 12
0.1 F
R1
3.32k
L
U2b
1/2
AD708
V =
O
V
IN
2
VO
Figure 13. Precision AGC Loop
Diode D1 and C1 form a peak detector, which rectifies the out-
put and causes the integrator to ramp positive. When the
current in R1 balances the current in R2, the integrator output
holds the denominator output at a constant value. This occurs
when there is sufficient gain to raise the amplitude of E
IN
to that
required to establish an output amplitude of E
C
over the range
of +1 V to +10 V. The X input of the AD734, which has finite
offset voltage, could be troublesome at the output at high gains.
The output offset is reduced to that of the X input (one or two
millivolts) by the offset loop comprising R3, C3, and buffer A1.
The low pass corner frequency of 0.16 Hz is transformed to a
high-pass corner that is multiplied by the gain (for example,
160 Hz at a gain of 1000).
In applications not requiring operation down to low frequencies,
amplifier A1 can he eliminated, but the AD734’s input
resistance of 50 kΩ between X1 and X2 will reduce the time
constant and increase the input offset. Using a non-polar 20
µF
tantalum capacitor for C1 will result in the same unity-gain
high-pass corner; in this case, the offset gain increases to 20, still
very acceptable.
Figure 14 shows the error in the output for sinusoidal inputs at
100 Hz, 100 kHz, and 1 MHz, with E
C
set to +10 V. The out-
put error for any frequency between 300 Hz and 300 kHz is
similar to that for 100 kHz. At low signal frequencies and low
input amplitudes, the dynamics of the control loop determine
the gain error and distortion; at high frequencies, the 200 MHz
gain-bandwidth product of the AD734 limit the available gain.
REV. C
U1
Z1 11
Z2 10
ER 9
VN 8
L
C1
47 F
L
0.1 F
L
–15V
C2
1 F
L
Figure 15. A 2-Chip, Wideband RMS-DC Converter
In this application, the AD734 and an AD708 dual op amp
serve as a 2-chip RMS-DC converter with a 10 MHz bandwidth.
Figure 16 shows the circuit’s performance for square-, sine-,
and triangle-wave inputs. The circuit accepts signals as high as
10 V p-p with a crest factor of 1 or 1 V p-p with a crest factor of
10. The circuit’s response is flat to 10 MHz with an input of
10 V, flat to almost 5 MHz for an input of 1 V, and to almost
1 MHz for inputs of 100 mV. For accurate measurements of
input levels below 100 mV, the AD734’s output offset (Z inter-
face) voltage, which contributes a dc error, must be trimmed out.
In Figure 15’s circuit, the AD734 squares the input signal, and
its output (V
IN2
) is averaged by a low-pass filter that consists of
R1 and C1 and has a corner frequency of 1 Hz. Because of the
implicit feedback loop, this value is both the output value, V
RMS
,
and the denominator in Equation (13). U2a and U2b, an
AD708 dual dc precision op amp, serve as unity-gain buffers,
supplying both the output voltage and driving the U interface.
–9–
AD [ ANALOG DEVICES ]
