AD73311
Table XI. Control Register A Description
CONTROL REGISTER A
7
6
5
4
3
2
1
0
DATA/
PGM
RESET
DC2
DC1
DC0
DLB
ALB
MM
Bit
Name
Description
0
1
2
3
4
5
6
7
DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)
MM
ALB
DLB
DC0
DC1
DC2
RESET
Mixed Mode (0 = Off; 1 = Enabled)
Analog Loop-Back Mode (0 = Off; 1 = Enabled)
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = Off; 1 = Initiates Reset)
Table XII. Control Register B Description
CONTROL REGISTER B
7
6
5
4
3
2
1
1
0
1
CEE
MCD2
MCD1
MCD0
SCD1
SCD0
Bit
Name
Description
0
1
2
3
4
5
6
7
Reserved
Reserved
SCD0
Must Be Programmed to 1
Must Be Programmed to 1
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
SCD1
MCD0
MCD1
MCD2
CEE
Control Echo Enable (0 = Off; 1 = Enabled)
Table XIII. Control Register C Description
7
6
5
4
3
2
0
1
0
0
CONTROL REGISTER C
5VEN
RU
PUREF PUDAC PUADC
PU
Bit
Name
Description
0
1
2
3
4
5
6
PU
Power-Up Device (0 = Power Down; 1 = Power On)
Must Be Programmed to 0
Must Be Programmed to 0
ADC Power (0 = Power Down; 1 = Power On)
DAC Power (0 = Power Down; 1 = Power On)
REF Power (0 = Power Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable
REFOUT)
Reserved
Reserved
PUADC
PUDAC
PUREF
RU
7
5VEN
Enable 5 V Operating Mode (0 = Disable 5 V Mode;
1 = Enable 5 V Mode)
REV. B
–17–
ADI [ ADI ]
