AD7237A/AD7247A
MICROPROCESSOR INTERFACING—AD7247A
AD7247A—MC68000 Interface
Figures 10 to 12 show interfaces between the AD7247A and
the ADSP-2101 DSP processor and the 8086 and 68000 16-bit
microprocessors. In all three interfaces, the AD7247A is
memory-mapped with a separate memory address for each DAC.
AD7247A—ADSP-2101 Interface
Figure 10 shows an interface between the AD7247A and the
ADSP-2101. The 12-bit word is written to the selected DAC
latch of the AD7247A in a single instruction, and the analog
output responds immediately. Depending on the clock fre-
quency of the ADSP-2101, either one or two wait states will
have to be programmed into the data memory wait state control
register of the ADSP-2101.
Interfacing between the AD7247A and the MC68000 micropro-
cessor is achieved using the circuit of Figure 12. Once again, the
12-bit word is written to the selected DAC latch of the
AD7247A in a single MOVE instruction.
CSA
and
CSB
have to
be AND-gated to provide a
DTACK
signal for the MC68000
when either DAC latch is selected.
Figure 12. AD7247A to MC68000 Interface
MICROPROCESSOR INTERFACING—AD7237A
Figure 10. AD7247A to ADSP-2101 Interface
AD7247A—8086 Interface
Figures 13 to 15 show the AD7237A configured for interfacing
to microprocessors with 8-bit databus systems. In all cases, data
is right-justified, and the AD7237A is memory-mapped with the
two lowest address lines of the microprocessor address bus driv-
ing the A0 and A1 inputs of the converter.
AD7237A—8085A/8088 Interface
Figure 11 shows an interface between the AD7247A and the
8086 microprocessor. The 12-bit word is written to the selected
DAC latch of the AD7247A in a single MOV instruction, and
the analog output responds immediately.
Figure 13 shows the connection diagram for interfacing the
AD7237A to both the 8085A and the 8088. This scheme is also
suited to the Z80 microprocessor, but the Z80 address/ databus
does not have to be demultiplexed. The AD7237A requires five
separate memory addresses, one for the each MS latch and one
for each LS latch and one for the common
LDAC
input. Data is
written to the respective input latch in two write operations.
Figure 11. AD7247A to 8086 Interface
Figure 13. AD7237A to 8085A/8088 Interface
REV. 0
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AD [ ANALOG DEVICES ]
