AD7224
BIPOLAR OUTPUT OPERATION
V
IN
The AD7224 can be configured to provide bipolar output op-
eration using one external amplifier and two resistors. Figure 6
shows a circuit used to implement offset binary coding. In this
case
R2
R2
V
O
=
1
+
•
(
D V
REF
)
–
•
(
V
REF
)
R1
R1
V
REF
V
DD
AGND
V
IN
V
BIAS
V
SS
DAC
V
OUT
AD7224
DGND
With
R1
=
R2
V
O
= (2
D
– 1) •
V
REF
where
D
is a fractional representation of the digital word in
the DAC register.
Mismatch between R1 and R2 causes gain and offset errors;
therefore, these resistors must match and track over tempera-
ture. Once again, the AD7224 can be operated in single supply
or from positive/negative supplies. Table III shows the digital
code versus output voltage relationship for the circuit of Figure
6 with R1 = R2.
V
REF
DB7
DATA
(8-BIT)
DB0
CS
WR
LDAC
RESET
V
SS
AGND
DGND
DAC
V
OUT
+15V
A15
Figure 7. AGND Bias Circuit
MICROPROCESSOR INTERFACE
A15
A8
ADDRESS BUS
8085A
8088
WR
ADDRESS
DECODE
CS
LDAC
AD7224*
WR
LATCH
EN
DB7
DB0
ADDRESS DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
V
REF
3
V
DD
R1
R2
+15V
V
OUT
ALE
AD7
AD0
Figure 8. AD7224 to 8085A/8088 Interface
ADDRESS BUS
A0
6809
6502
R/W
ADDRESS
DECODE
EN
CS
LDAC
AD7224
R1, R2 = 10kΩ
±0.1%
Figure 6. Bipolar Output Circuit
E OR
φ2
AD7224*
WR
DB7
DB0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
D7
E OR
φ2
D0
D7
Table III. Bipolar (Offset Binary) Code Table
DAC Register Contents
MSB
LSB
1111
1000
1000
0111
0000
0000
1111
0001
0000
1111
0001
0000
Analog Output
127
+V
REF
128
1
+V
REF
128
D0
Figure 9. AD7224 to 6809/6502 Interface
A15
ADDRESS BUS
A0
0V
Z-80
CS
ADDRESS
DECODE
LDAC
1
–V
REF
128
127
–V
REF
128
128
–V
REF
=
–V
REF
128
AD7224*
WR
WR
DB7
DB0
D7
D0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
AGND BIAS
Figure 10. AD7224 to Z-80 Interface
A23
ADDRESS BUS
A1
68008
ADDRESS
DECODE
CS
LDAC
WR
The AD7224 AGND pin can be biased above system GND
(AD7224 DGND) to provide an offset “zero” analog output
voltage level. Figure 7 shows a circuit configuration to achieve
this. The output voltage, V
OUT
, is expressed as:
V
OUT
=
V
BIAS
+
D
•
(V
IN
)
where
D
is a fractional representation of the digital word in
DAC register and can vary from 0 to 255/256.
For a given V
IN
, increasing AGND above system GND will re-
duce the effective V
DD
–V
REF
which must be at least 4 V to en-
sure specified operation. Note that V
DD
and V
SS
for the AD7224
must be referenced to DGND.
REV. B
–7–
R/W
DTACK
AD7224*
DB7
DB0
D7
D0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 11. AD7224 to 68008 Interface
AD [ ANALOG DEVICES ]
