AD7002
CLK1, CLK2 (I)
t23
t25
t24
Rx SLEEP1 (I)
Rx SLEEP2 (I)
t28
t26
t30
t27
Rx CLK (O)
Rx SYNC (O)
Rx DATA (O)
t29
t31
t33
t32
t34
I LSB
I MSB
Q MSB
Q LSB
I MSB
I LSB
Q MSB
Q LSB
t35
t35
I/Q (O)
NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT
Figure 16. MODE 0 RATE 1 Receive Timing
CLK1, CLK2 (I)
t23
t25
t24
Rx SLEEP1 (I)
Rx SLEEP2 (I)
t26
t28
t
t30
27
Rx CLK (O)
t31
t33
t29
Rx SYNC (O)
t32
t34
Rx DATA (O)
I/Q (O)
I MSB
I LSB
Q MSB
Q LSB
I MSB
I LSB
Q MSB
Q LSB
t35
t35
NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT
Figure 17. MODE 0 RATE 0 Receive Timing
CLK1, CLK2 (I)
t23
t25
t24
Rx SLEEP1 (I)
Rx SLEEP2 (I)
t30
t27
t26
t31
t
28
Rx CLK (O)
Rx SYNC (O)
I DATA (O)
t29
t33
t32
t34
I MSB
I LSB
I MSB
I LSB
t34
Q MSB
Q LSB
Q MSB
Q LSB
Q DATA (O)
NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT
Figure 18. MODE 1 RATE 1 Receive Timing
REV. B
–13–