AD677
PIN DESCRIPTION
DIP Pin
1
SOIC Pin
1
Type
SAMPLE
Name
DI
Description
V
IN
Acquisition Control Pin. Active HIGH. During conversion, SAMPLE
controls the suite of the internal sample-hold amplifier and the falling edge
initiates conversion. During calibration, SAMPLE should be held LOW. If
HIGH during calibration, diagnostic information will appear on SDATA.
Master Clock Input. The AD677 requires 17 clock pulses to execute a
conversion. CLK is also used to derive SCLK.
Serial Output Data Controlled by SCLK.
Digital Ground.
+12 V Analog Supply Voltage.
Analog Ground.
Analog Ground Sense.
Analog Input Voltage.
External Voltage Reference Input.
–12 V Analog Supply Voltage.
+5 V Logic Supply Voltage.
Clock Output for Data Read, derived from CLK.
Status Line for Converter. Active HIGH, indicating a conversion or
calibration in progress.
Calibration Control Pin.
No Connection. No connections should be made to these pins.
2
3
4
5
8
.9
10
11
12
13
14
15
16
6, 7
2
3
6, 7
8
12
15
16
17
21
22, 23
26
27
28
4, 5, 9, 10, 11,
13, 14, 18, 19,
20, 24, 25
CLK
SDATA
DGND
V
CC
AGND
AGND SENSE
V
IN
V
REF
V
EE
V
DD
SCLK
BUSY
CAL
NC
DI
DO
P
P
P
AI
AI
AI
P
P
DO
DO
DI
_
Type: AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
SAMPLE
CLK
SDATA
DGND
V
CC
NC
NC
AGND
1
2
3
4
5
6
7
8
NC = NO CONNECT
16 CAL
15 BUSY
14
SCLK
V
DD
V
EE
V
REF
SAMPLE
CLK
SDATA
NC
NC
DGND1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
CAL
BUSY
SCLK
NC
NC
V
DD1
V
DD2
V
EE
NC
NC
NC
V
REF
V
IN
AGND
SENSE
AD677
TOP VIEW
(Not to Scale)
13
12
11
DGND2
10 V
IN
9
AGND
SENSE
AD677
TOP VIEW
(Not to Scale)
22
21
20
19
18
17
16
15
V
CC
NC
NC
NC
AGND
NC
NC
DIP Pinout
NC = NO CONNECT
SOIC Pinout
–6–
REV. A
AD [ ANALOG DEVICES ]
