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AD677JR 参数 Datasheet PDF下载

AD677JR图片预览
型号: AD677JR
PDF下载: 下载PDF文件 查看货源
内容描述: 16位100 kSPS的采样ADC [16-Bit 100 kSPS Sampling ADC]
分类和应用: 转换器模数转换器光电二极管信息通信管理
文件页数/大小: 16 页 / 430 K
品牌: AD [ ANALOG DEVICES ]
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AD677
The standard deviation of this distribution is approximately
0.5 LSBs. If less uncertainty is desired, averaging multiple con-
versions will narrow this distribution by the inverse of the square
root of the number of samples; i.e., the average of 4 conversions
would have a standard deviation of 0.25 LSBs.
dB
105
100
90
80
70
THD
DSP INTERFACE
Figure 10 illustrates the use of the Analog Devices ADSP-2101
digital signal processor with the AD677. The ADSP-2101 FO
(flag out) pin of Serial Port 1 (SPORT 1) is connected to the
SAMPLE line and is used to control acquisition of data. The
ADSP-2101 timer is used to provide precise timing of the FO
pin.
ADSP-2101
FO
SCLK0
DR0
SERIAL
PORT 0
RFS0
DT0
TFS0
AMPLITUDE – dB
60
50
40
30
20
10
–80
S/(N+D)
–70
–60
–50
–40
–30
–20
–10
0
AD677
SAMPLE
CLK
SDATA
BUSY
0
–20
–40
–60
–80
–100
–120
–140
0
5
10
15
INPUT LEVEL – dB
Figure 12. S/(N+D) and THD vs. Input Amplitude,
f
S
= 100 kHz
Figure 10. ADSP-2101 Interface
AMPLITUDE – dB
The SCLK pin of the ADSP-2101 SPORT0 provides the CLK
input for the AD677. The clock should be programmed to be
approximately 2 MHz to comply with AD677 specifications. To
minimize digital feedthrough, the clock should be disabled (by
setting Bit 14 in SPORT0 control register to 0) during data ac-
quisition. Since the clock floats when disabled, a pulldown resis-
tor of 12 kΩ–15 kΩ should be connected to SCLK to ensure it
will be LOW at the falling edge of SAMPLE. To maximize the
conversion rate, the serial clock should be enabled immediately
after SAMPLE is brought LOW (hold mode).
The AD677 BUSY signal is connected to RF0 to notify
SPORT0 when a new data word is coming. SPORT0 should be
configured in normal, external, noninverting framing mode and
can be programmed to generate an interrupt after the last data
bit is received. To maximize the conversion rate, SAMPLE
should be brought HIGH immediately after the last data bit is
received.
106
20
25
30
FREQUENCY – kHz
35
40
45
50
Figure 13. 4096 Point FFT at 100 kSPS, f
IN
= 1 kHz,
V
REF
= 5 V
0
–20
–40
–60
–80
–100
–120
–140
0
5
10
15
20
25
30
FREQUENCY – kHz
35
40
45
48
Figure 14. 4096 Point FFT at 100 kSPS, f
IN
= 1 kHz,
V
REF
= 10 V
THD
102
98
dB
94
S/(N+D)
90
86
82
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.0
V
REF
– Volts
Figure 11. S/(N+D) and THD vs. V
REF
, f
S
= 100 kHz (Calibra-
tion is not guaranteed below +5 V
REF
)
REV. A
–13–