AD667
Model
AD667A
Min
Typ
Max
Min
AD667B
Typ
Max
Min
AD667S
Typ
Max
Units
DIGITAL INPUTS
Resolution
Logic Levels (TTL, Compatible, T
MIN
–T
MAX
)
1
V
IH
(Logic “l’’)
V
IL
(Logic “0”)
I
IH
(V
IH
= 5.5 V)
I
IL
(V
IL
= 0.8 V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ +25°C
T
A
= T
MIN
to T
MAX
Differential Linearity Error @ +25°C
T
A
= T
MIN
to T
MAX
Gain Error
2
Unipolar Offset Error
2
Bipolar Zero
2
DRIFT
Differential Linearity
Gain (Full Scale) T
A
= 25°C to T
MIN
or T
MAX
Unipolar Offset T
A
= 25°C to T
MIN
or T
MAX
Bipolar Zero T
A
= 25°C to T
MIN
or T
MAX
CONVERSION SPEED
Settling Time to
±
0.01% of FSR for
FSR Change (2 kΩ 500 pF Load)
with 10 kΩ Feedback
with 5 kΩ Feedback
For LSB Change
Slew Rate
ANALOG OUTPUT
Ranges
4
Output Current
Output Impedance (DC)
Short Circuit Current
REFERENCE OUTPUT
External Current
POWER SUPPLY SENSITIVITY
V
CC
= +11.4 V to +16.5 V dc
V
EE
= –11.4 V to –16.5 V dc
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
4
Supply Current
+11.4 V to +16.5 V dc
–11.4 V to –16.5 V dc
TEMPERATURE RANGE
Specification
Storage
±
5
12
+2.0
0
3
1
+5.5
+0.8
10
5
+2.0
0
3
1
12
+5.5
+0.8
10
5
+2.0
0
3
1
12
+5.5
+0.7
10
5
Bits
V
V
µA
µA
+1/4
1/2
±
1/2
3/4
±
1/2
3/4
Monotonicity Guaranteed
±
0.1
0.2
±
1
2
±
0.05
0.1
±
2
±
5
±
1
±
5
±
1/8
1/4
±
1/4
1/2
±
1/4
1/2
Monotonicity Guaranteed
±
0.1
0.2
±
1
2
±
0.05
0.1
±
2
±
5
±
1/8
1/2
±
1/8
3/4
±
1/4
3/4
Monotonicity Guaranteed
±
0.1
0.2
±
1
2
±
0.05
0.1
±
2
±
15
LSB
LSB
LSB
LSB
% FSR
3
LSB
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
±
30
±
3
±
10
±
15
±
3
±
10
30
3
10
3
2
1
10
4
3
10
3
2
1
4
3
10
3
2
1
4
3
µs
µs
µs
V/µs
V
mA
Ω
mA
V
mA
ppm of FS/%
ppm of FS/%
V
V
mA
mA
°C
°C
±
2.5,
±
5,
±
10,
+5, +10
0.05
40
±
5
±
2.5,
±
5,
±
10,
+5, +10
0.05
40
±
5
±
2.5,
±
5,
±
10,
+5, +10
0.05
40
9.90
0.1
10.00
1.0
5
5
±
12,
±
15
10.10
9.90
0.1
10.00
1.0
5
5
±
12,
±
15
10.10
9.90
1.0
10.00
10.10
10
10
10
10
5
5
±
12,
±
15
10
10
11.4
8
20
–25
–65
16.5
12
25
+85
+150
11.4
8
20
–25
–65
16.5
12
25
+85
+150
11.4
8
20
–55
–65
16.5
12
25
+125
+150
TIMING DIAGRAMS
WRITE CYCLE #1
WRITE CYCLE #2
(Load Second Rank from First Rank; A2, A1, A0 = 1)
(Load First Rank from Data Bus; A3 = 1)
REV. A
–3–
AD [ ANALOG DEVICES ]
