AD6640
the device. A full-scale transition can cause up to 120 mA
(12 bits × 10 mA/bit) of current to flow through the digital
output stages. T he series resistor will minimize the output
currents that can flow in the output stage. T hese switching
currents are confined between ground and the DVCC pin. Stan-
dard T T L gates should be avoided since they can appreciably
add to the dynamic switching currents of the AD6640.
the sides should be implemented. The addition of small value
resistors between the AD9631 and the AD6640 will prevent
oscillation due to the capacitive input of the ADC.
AD9631
62⍀
SIGNAL
15⍀
SOURCE
AIN
467⍀
78⍀
350⍀
AD6640
Layout Infor m ation
1000⍀
T he schematic of the evaluation board (Figure 36) represents a
typical implementation of the AD6640. T he pinout of the
AD6640 facilitates ease of use and the implementation of high
frequency/high resolution design practices. All of the digital
outputs are on one side while the other sides contain all of the
inputs. It is highly recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground di-
rectly at the device. Depending on the configuration used for
the encode and analog inputs, one or more capacitors are required
on those input pins. The capacitors used on the ENCODE and
VREF pins must be a low inductance chip capacitor as referenced
previously in the data sheet.
OP279
(1/2)
OP279
(1/2)
V
750⍀
425⍀
REF
0.1F
0.01F
0.1F
350⍀
467⍀
350⍀
15⍀
AIN
127⍀
AD9631
Figure 35. DC-Coupled Analog Input Circuit
A multilayer board is recommended to achieve best results. Care
should be taken when placing the digital output runs. Because
the digital outputs have such a high slew rate, the capacitive
loading on the digital outputs should be minimized. Circuit
traces for the digital outputs should be kept short and connect
directly to the receiving gate (broken only by the insertion of the
series resistor). Digital data lines should be kept clear of analog
and encode traces.
P ower Supplies
Care should be taken when selecting a power source. Linear
supplies are strongly recommended as switching supplies tend to
have radiated components that may be “received” by the
AD6640. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 µF chip capacitors.
T he AD6640 has separate digital and analog +5 V pins. T he
analog supplies are denoted AVCC and the digital supply pins
are denoted DVCC. Although analog and digital supplies may be
tied together, best performance is achieved when the supplies
are separate. T his is because the fast digital output swings can
couple switching noise back into the analog supplies. Note that
AVCC must be held within 5% of 5 volts; however the DVCC
supply may be varied according to output digital logic family
(i.e., DVCC should be connected to the same supply as the digi-
tal circuitry). T he AD6640 is specified for DVCC = 3.3 V as this
is a common supply for digital ASICs.
Evaluation Boar ds
T he evaluation board for the AD6640 is very straightforward,
consisting of power, signal inputs and digital outputs. T he
evaluation board includes the option for an onboard clock oscil-
lator for the encode.
Power to the analog supply pins is connected via banana jacks.
T he analog supply powers the crystal oscillator and the AVCC
pins of the AD6640.
T he DVCC power is supplied via J3, the digital interface. T his
digital supply connection also powers the digital gates on the
PCB. By maintaining separate analog and digital power supplies,
degradation in SNR and SFDR is kept to a minimum. T otal
power requirement is approximately 200 mA. This configuration
allows for easy evaluation of different logic families (i.e., con-
nection to a 3.3 volt logic board).
O utput Loading
Care must be taken when designing the data receivers for the
AD6640. It is recommended that the digital outputs drive a
series resistor (e.g. 348 ohms) followed by a gate like the
74LCX574. T o minimize capacitive loading, there should only
be one gate on each output pin. An example of this is shown in
the evaluation board schematic shown in Figure 36. T he digital
outputs of the AD6640 have a constant rise time output stage.
T he output slew rate is about 1 V/ns when DVCC = +5 V. A
typical CMOS gate combined with PCB trace and through hole
will have a load of approximately 10 pF. T herefore as each bit
switches, 10 mA
T he analog input is connected via J2 and is transformer-coupled
to the AD6640 (see Driving the Analog Input). T he onboard
termination resistor is 270 Ω. T his resistor, in parallel with the
AD6640’s input resistance (900 Ω), provides a 50 Ω load to the
analog source driving the 1:4 transformer. If a different input
impedance is required, replace R16 by using the following
equation
1V
1ns
1
10 pF ×
R16 =
of dynamic current per bit will flow in or out of
1
1
−
Z
900
where Z is desired input impedance (200 Ω for a 4:1 trans-
former with 50 Ω source).
REV. 0
–13–
ADI [ ADI ]
