AD6600–SPECIFICATIONS
DC SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40ꢂC, TMAX = +85ꢂC unless otherwise noted.)
Test
Level
AD6600AST
Typ
Parameter
Temp
Min
Max
Unit
ANALOG INPUTS (AIN, AIN/BIN, BIN)
Differential Analog Input Voltage Range1
Differential Analog Input Resistance2
Differential Analog Input Capacitance
Full
Full
25°C
V
IV
V
2.0
200
1.5
V p-p
Ω
pF
160
240
PEAK DETECTOR (Internal), RSSI
Resolution
3
6
6
Bits
dB
dB
RSSI Gain Step
Full
Full
V
V
RSSI Hysteresis3
RESONANT PORT (FLT, FLT)
Differential Port Resistance
Differential Port Capacitance
Full
Full
V
V
630
1.75
Ω
pF
A/D CONVERTER
Resolution
Full
IV
11
Bits
ENCODE INPUTS (ENC, ENC)
Differential Input Voltage (AC-Coupled)4
Differential Input Resistance
Differential Input Capacitance
A/B MODE INPUTS (A_SEL, B_SEL)5
Input High Voltage Range
Full
IV
V
V
0.4
V p-p
kΩ
25°C
11
2.5
25°C
pF
Full
Full
IV
IV
4.75
0.0
5.25
0.5
V
V
Input Low Voltage Range
POWER SUPPLY
Supply Voltages
AVCC
Full
Full
II
IV
4.75
3.0
5.0
3.3
5.25
5.25
V
V
DVCC
Supply Current
I
AVCC (AVCC = 5.0 V)
Full
Full
II
II
145
15
182
20
mA
mA
IDVCC (DVCC = 3.3 V)
POWER CONSUMPTION6
NOTES
Full
II
775
976
mW
1Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs.
2Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.
3Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations.
4Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.
5A_SEL and B_SEL should be tied directly to ground or AVCC.
6Maximum power consumption is computed as maximum current at nominal supplies.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; T
MIN = –40ꢂC, TMAX = +85ꢂC unless otherwise noted.)
Test
AD6600AST
Typ
Parameter
Temp
Level
Min
Max
Unit
LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)1
Logic Compatibility
CMOS
Logic “1” Voltage (DVCC = 3.3 V)
Logic “0” Voltage (DVCC = 3.3 V)
Logic “1” Voltage (DVCC = 5.0 V)
Logic “0” Voltage (DVCC = 5.0 V)
Output Coding (D10–D0)
Full
Full
Full
Full
II
II
IV
IV
2.8
4.0
DVCC – 0.2
V
V
V
V
0.2
0.5
0.5
DVCC – 0.35
0.35
Two’s Complement
CLK2× OUTPUT1, 2
Logic “1” Voltage (DVCC = 3.3 V)
Logic “0” Voltage (DVCC = 3.3 V)
Logic “1” Voltage (DVCC = 5.0 V)
Logic “0” Voltage (DVCC = 5.0 V)
Full
Full
Full
Full
II
2.8
4.0
DVCC – 0.2
0.2
DVCC – 0.3
0.35
V
V
V
V
II
0.5
0.5
IV
IV
NOTES
1Digital output load is one LCX gate.
2CLK2× output voltage levels, high and low, tested at switching rate of 10 MHz.
Specifications subject to change without notice.
–2–
REV. 0
ADI [ ADI ]
