AD652
The choice of an integrating capacitor is primarily dictated by
DELTA MODULATOR
the input signal bandwidth. Figure 37 shows this relationship.
Note that as the value of CINT is lowered, the ramp size of the
integrator approximation becomes larger. This can be
compensated for by increasing the clock frequency. The effect of
the clock frequency on the ramp size is demonstrated in
Figure 35 and Figure 36.
The circuit of Figure 34 shows the AD652 configured as a delta
modulator. A reference voltage is applied to the input of the
integrator (Pin 7), which sets the steady state output frequency
at one-half of the AD652 full-scale frequency (1/4 of the clock
frequency). As a 0 V to 10 V input signal is applied to the
comparator (Pin 15), the output of the integrator attempts to
track this signal. For an input in an idling condition (dc), the
output frequency is one-half full scale. For positive-going
signals, the output frequency is between one-half full scale and
full scale; for negative-going signals, the output frequency is
between zero and one-half full scale. The output frequency
corresponds to the slope of the comparator input signal.
AD652
SYNCHRONOUS
VOLTAGE-TO-
5V
1
2
3
4
5
6
7
8
FREQUENCY
CONVERTER
16
15
14
13
12
11
10
9
+15V
REFERENCE
V
(0V TO 10V)
IN
Figure 35. Delta Modulator Input Signal and Ramp-Wise Approximation
+5V
1kΩ
360pF
ONE
SHOT
0.01µF
CLOCK
F
20kΩ
OUT
1mA
Q
CK
–15V
D
AND
"D"
FLOP
Q
0.0047µF
Figure 34. Delta Modulator
Since the output frequency corresponds to the slope of the input
signal, the delta modulator acts as a differentiator. A delta
modulator is thus a direct way of finding the derivative of a
signal. This is useful in systems where, for example, a signal
corresponding to velocity exists, and it is desired to determine
acceleration.
Figure 36. Delta Modulator Input Signal Ramp-Wise Approximation and
Output Frequency
Figure 35 is a scope photo showing a 20 kHz, 0 V to 10 V sine
wave used as the input to the comparator and its ramp-wise
approximation at the integrator output. The clock frequency
used as 2 MHz and the integrating capacitor was 360 pF.
Figure 36 shows the same input signal and its ramp-wise
approximation, along with the output frequency corresponding
to the derivative of the input signal. In this case, the clock
frequency was 50 kHz.
10k
1k
100
100
1k
10k
INPUT SIGNAL BANDWIDTH (Hz)
Figure 37. Maximum Integrating Cap Value vs. Input Signal Bandwidth
Rev. C | Page 23 of 28
ADI [ ADI ]
