AD628
APPLICATIONS INFORMATION
GAIN ADJUSTMENT
INPUT VOLTAGE RANGE
VREF and the supply voltage determine the common-mode
input voltage range. The relation is expressed by
The AD628 system gain is provided by an architecture
consisting of two amplifiers (see Figure 29). The gain of the
input stage is fixed at 0.1; the output buffer is user adjustable
as GA2 = 1 + REXT1/REXT2. The system gain is then
VCM
≤11(VS+ –1.2 V) −10 VREF
≥11(VS− +1.2 V) −10 VREF
(2)
UPPER
VCM
LOWER
⎛
⎞
⎟
⎟
⎠
REXT1
REXT2
⎜
GTOTAL = 0.1× 1+
(1)
where:
VS+ is the positive supply.
⎜
⎝
At a 2 nA maximum, the input bias current of the buffer amplifier
is very low and any offset voltage induced at the buffer amplifier
by its bias current may be neglected (2 nA × 10 kΩ = 20 μV).
However, to absolutely minimize bias current effects, select
VS− is the negative supply.
1.2 V is the headroom needed for suitable performance.
Equation 2 provides a general formula for calculating the
common-mode input voltage range. However, keep the AD628
within the maximum limits listed in Table 1 to maintain
optimal performance. This is illustrated in Figure 30 where the
maximum common-mode input voltage is limited to 120 V.
Figure 31 shows the common-mode input voltage bounds for
single-supply voltages.
REXT1 and REXT2 so that their parallel combination is 10 kΩ. If
practical resistor values force the parallel combination of REXT1
and REXT2 below 10 kΩ, add a series resistor (REXT3) to make up
for the difference. Table 5 lists several values of gain and
corresponding resistor values.
200
Table 5. Nearest Standard 1% Resistor Values for
Various Gains (see Figure 29)
150
100
50
Total Gain
(V/V)
A2 Gain
(V/V)
REXT1 (Ω)
10 k
20 k
25.9 k
49.9 k
100 k
200 k
499 k
1 M
REXT2 (Ω)
∞
20 k
18.7 k
12.4 k
11 k
REXT3 (Ω)
0.1
0.2
0.25
0.5
1
1
2
0
0
0
0
0
0
0
0
MAXIMUM INPUT COMMON-MODE
0
2.5
5
10
20
50
100
VOLTAGE WHEN V
= GND
REF
–50
–100
–150
–200
2
5
10
10.5 k
10.2 k
10.2 k
0
2
4
6
8
10
12
14
16
To set the system gain to <0.1, create an attenuator by placing
Resistor REXT4 from Pin 4 (CFILT) to the reference voltage. A
divider is formed by the 10 kΩ resistor that is in series with the
positive input of A2 and Resistor REXT4. A2 is configured for
unity gain.
SUPPLY VOLTAGE (±V)
Figure 30. Input Common-Mode Voltage vs. Supply Voltage
for Dual Supplies
100
80
Using a divider and setting A2 to unity gain yields
60
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
40
REXT4
10 kꢁ + REXT4
GW /DIVIDER = 0.1×
×1
20
MAXIMUM INPUT COMMON-MODE
0
–20
–40
–60
–80
VOLTAGE WHEN V
= MIDSUPPLY
REF
0
2
4
6
8
10
12
14
16
SINGLE-SUPPLY VOLTAGE (V)
Figure 31. Input Common-Mode Voltage vs.
Supply Voltage for Single Supplies
Rev. G | Page 16 of 20
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