AD626
100
90
100
90
10
0%
10
0%
TPC 25. Settling Time. V
S
= +5 V, G = 10
TPC 26. Settling Time. V
S
= +5 V, G = 100
ERROR
OUT
10k
2k
+V
S
INPUT
20V p–p
10k
1k
10k
AD626
–V
S
Figure 4 shows the main elements of the AD626. The signal inputs
at Pins 1 and 8 are first applied to dual resistive attenuators R1
through R4 whose purpose is to reduce the peak common-mode
voltage at the input to the preamplifier—a feedback stage based
on the very low drift op amp A1. This allows the differential
input voltage to be accurately amplified in the presence of large
common-mode voltages six times greater than that which can be
tolerated by the actual input to A1. As a result, the input CMR
extends to six times the quantity (V
S
– 1 V). The overall common-
mode error is minimized by precise laser-trimming of R3 and R4,
thus giving the AD626 a common-mode rejection ratio (CMRR)
of at least 10,000:1 (80 dB).
To minimize the effect of spurious RF signals at the inputs due to
rectification at the input to A1, small filter capacitors C1 and C2
are included.
The output of A1 is connected to the input of A2 via a 100 k
(R12) resistor to facilitate the low-pass filtering of the signal of
interest (see Low-Pass Filtering section).
The 200 k input impedance of the AD626 requires that the source
resistance driving this amplifier be low in value (<1 k )—this is
Figure 3. Settling Time Test Circuit
THEORY OF OPERATION
The AD626 is a differential amplifier consisting of a precision
balanced attenuator, a very low drift preamplifier (A1), and an
output buffer amplifier (A2). It has been designed so that small
differential signals can be accurately amplified and filtered in the
presence of large common-mode voltages (V
CM
), without the use
of any other active components.
+V
S
FILTER
R1
200k
+IN
C1
5pF
R12
100k
A1
AD626
–IN
R2
200k
R3
41k
C2
5pF
R4
41k
R17
95k
R9
10k
R10
10k
A2
OUT
R15
10k
R11
10k
R6
500
R5
4.2k
R7
500
R8
10k
R14
555
R13
10k
GND
GAIN = 100
–V
S
Figure 4. Simplified Schematic
REV. D
–9–
AD [ ANALOG DEVICES ]
