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AD608AR-REEL 参数 Datasheet PDF下载

AD608AR-REEL图片预览
型号: AD608AR-REEL
PDF下载: 下载PDF文件 查看货源
内容描述: 低功率混频器/限制器/ RSSI 3 V接收器IF子系统 [Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem]
分类和应用: 射频微波限制器局域网
文件页数/大小: 16 页 / 326 K
品牌: AD [ ANALOG DEVICES ]
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AD608
THEORY OF OPERATION
The AD608 consists of a mixer followed by a logarithmic IF
strip with RSSI and hard-limited outputs (see Figure 22).
MIXER GAIN
The conversion gain of the mixer is the product of its trans-
conductance and the impedance seen at Pin MXOP. For a 330 Ω
parallel-terminated filter at 10.7 MHz, the load impedance is
165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV (or
±891 mV) centered on the midpoint of the supply voltage. For
other load impedances, the expression for the gain in decibels is
G
dB
= 20 log
10
(0.0961
R
L
)
where:
G
dB
is the gain in decibels.
R
L
is the load impedance at Pin MXOP.
The gain of the mixer can be increased or decreased by changing
R
L
. The limitations on the gain are the ±6 mA maximum output
current at MXOP and the maximum allowable voltage swing at
Pin MXOP, which is ±1.0 V for a 3 V supply or 5 V supply.
MIXER
The mixer is a doubly balanced, modified gilbert-cell mixer. Its
maximum input level for linear operation is either ±56.2 mV,
regardless of the impedance across the mixer inputs, or −15 dBm
for a 50 Ω input termination. The input impedance of the mixer
can be modeled as a simple parallel RC network; the resistance
and capacitance values vs. frequency are listed in Table 5. The
bandwidth from the RF input to the IF output at the MXOP pin
is −1 dB at 30 MHz and then rapidly decreases as frequency
increases (see Figure 4).
24dB MIXER GAIN
3dB NOMINAL
INSERTION LOSS
IF INPUT
–75dBm TO
+15dBm
2
10.7MHz
BAND-PASS
FILTER
330Ω
8
110dB LIMITER GAIN
90dB RSSI
7 FULL-WAVE
RECTIFIER CELLS
IFHI
9
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
RFHI
RF INPUT
–95dBm TO
–15dBm
1
RFLO
6
5
RSSI
2MHz
LPF
11
20mV/dB
RSSI OUTPUT
0.2V TO 1.8V
MIXER
COM3
12
VPS2
14
2.7V TO 5.5V
15
MXOP
BPF
DRIVER
7
330Ω
10nF
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
10
LMOP
FINAL
LIMITER
LO
PREAMP
MIDSUPPLY
IF BIAS
BIAS
VPS1 COM1
1
2
3
100nF
+
100Ω
+
VMID
LIMITER
OUTPUT
400mV p-p
IFLO
13
18nF
+
FDBK
AD608
±50µA
LOHI COM2
4
16
PRUP
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
07886-022
1
–15dBm =
±56mV
MAXIMUM FOR LINEAR OPERATION.
2
39.76µV RMS TO 397.6mV RMS FOR
±1dB
RSSI ACCURACY.
Figure 22. Functional Block Diagram
Table 5. Mixer Input Impedance vs. Frequency
Frequency (MHz)
45
70
100
200
300
400
500
Resistance (Ω)
2800
2600
1900
1200
760
520
330
Capacitance (pF)
3.1
3.1
3.0
3.1
3.2
3.4
3.6
Rev. C | Page 9 of 16