AD603
2.0
1.5
1.0
GAIN ERROR (dB)
IS/N RATIO (dB)
00539-042
90
85
80
75
70
65
60
55
00539-044
00539-045
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.2
0
0.2
0.4
0.6
0.8
1.0
V
C
1.2
1.4
1.6
1.8
2.0
2.2
50
–0.2
0
0.2
0.4
V
C
0.6
0.8
1.0
1.2
Figure 42. Gain Error for Cascaded Stages–Sequential Control
Figure 44. ISNR for Cascaded Stages—Parallel Control
PARALLEL MODE (SIMPLEST GAIN CONTROL
INTERFACE)
In this mode, the gain control of voltage is applied to both
inputs in parallel—the GPOS pins of both A1 and A2 are
connected to the control voltage and the GNEW inputs are
grounded. The gain scaling is then doubled to 80 dB/V,
requiring only a 1.00 V change for an 80 dB change of gain:
Gain
= (dB) = 80
V
G
+
G
O
(4)
LOW GAIN RIPPLE MODE (MINIMUM GAIN ERROR)
As can be seen in Figure 42 and Figure 43, the error in the gain
is periodic, that is, it shows a small ripple. (Note that there is
also a variation in the output offset voltage, which is due to the
gain interpolation, but this is not exact in amplitude.) By
offsetting the gains of A1 and A2 by half the period of the
ripple, that is, by 3 dB, the residual gain errors of the two
amplifiers can be made to cancel. Figure 45 shows much lower
gain ripple when configured in this manner. Figure 46 plots the
ISNR as a function of gain; it is very similar to that in the
parallel mode.
3.0
2.5
2.0
where, as before, G
O
depends on the range selected; for example,
in the maximum bandwidth mode, G
O
is +20 dB. Alternatively,
the GNEG pins may be connected to an offset voltage of
0.500 V, in which case G
O
is −20 dB.
The amplitude of the gain ripple in this case is also doubled, as
shown in Figure 43, while the instantaneous signal-to-noise
ratio at the output of A2 now decreases linearly as the gain
increases, as shown in Figure 44.
2.0
1.5
1.0
GAIN ERROR (dB)
1.5
GAIN ERROR (dB)
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
0.5
0
–0.5
–1.0
–1.5
00539-043
–3.0
–0.1
0
0.1
0.2
0.3
0.4
0.5
V
C
0.6
0.7
0.8
0.9
1.0
1.1
Figure 45. Gain Error for Cascaded Stages—Low Ripple Mode
–2.0
–0.2
0
0.2
0.4
0.6
0.8
1.0
V
C
1.2
1.4
1.6
1.8
2.0
2.2
Figure 43. Gain Error for Cascaded Stages—Parallel Control
Rev. G | Page 16 of 20