AD603
The Gain-Control Interface
The attenuation is controlled through a differential, high-
impedance (50 MΩ) input, with a scaling factor which is
laser-trimmed to 40 dB per volt, that is, 25 mV/dB. An internal
bandgap reference ensures stability of the scaling with respect to
supply and temperature variations.
When the differential input voltage V
G
= 0 V, the attenuator
“slider” is centered, providing an attenuation of 21.07 dB. For
the maximum bandwidth range, this results in an overall gain of
10 dB (= –21.07 dB + 31.07 dB). When the control input is
–500 mV, the gain is lowered by 20 dB (= 0.500 V
×
40 dB/V),
to –10 dB; when set to +500 mV, the gain is increased by 20 dB, to
30 dB. When this interface is overdriven in either direction, the
gain approaches either –11.07 dB (= – 42.14 dB + 31.07 dB) or
31.07 dB (= 0 + 31.07 dB), respectively. The only constraint on
the gain-control voltage is that it be kept within the common-mode
range (–1.2 V to +2.0 V assuming +5 V supplies) of the gain
control interface.
The basic gain of the AD603 can thus be calculated using the
following simple expression:
Gain (dB) =
40
V
G
+ 10
(1)
where
V
G
is in volts. When Pins 5 and 7 are strapped (see next
section) the gain becomes
Gain (dB) =
40
V
G
+ 20
for
0
to
+40
dB
and
Gain (dB) =
40
V
G
+ 30
for
+10
to
+50
dB
(2)
The high impedance gain-control input ensures minimal loading
when driving many amplifiers in multiple channel or cascaded
applications. The differential capability provides flexibility in
choosing the appropriate signal levels and polarities for various
control schemes.
For example, if the gain is to be controlled by a DAC providing
a positive only ground-referenced output, the “Gain Control
LO” (GNEG) pin should be biased to a fixed offset of +500 mV,
to set the gain to –10 dB when “Gain Control HI” (GPOS) is at
zero, and to 30 dB when at +1.00 V.
It is a simple matter to include a voltage divider to achieve other
scaling factors. When using an 8-bit DAC having an FS output
of +2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)
would result in a gain-setting resolution of 0.2 dB/bit. The use
of such offsets is valuable when two AD603s are cascaded, when
various options exist for optimizing the S/N profile, as will be
shown later.
Programming the Fixed-Gain Amplifier Using Pin Strapping
DECIBELS
VC1
GPOS
VPOS
VPOS
AD603
VC2
GNEG
V
OUT
VNEG
VNEG
V
OUT
V
IN
VINP
COMM
FDBK
a. –10 dB to +30 dB; 90 MHz Bandwidth
VC1
GPOS
VPOS
VPOS
AD603
VC2
GNEG
V
OUT
VNEG
VNEG
2.15k
COMM
FDBK
5.6pF
V
OUT
V
IN
VINP
b. 0 dB to +40 dB; 30 MHz Bandwidth
VC1
GPOS
VPOS
VPOS
AD603
VC2
GNEG
V
OUT
VNEG
VNEG
V
OUT
V
IN
VINP
COMM
FDBK
18pF
c. +10 dB to +50 dB; 9 MHz Bandwidth
Figure 2. Pin Strapping to Set Gain
52
50
48
46
44
42
40
38
36
34
32
30
10
100
1k
R
EXT
10k
100k
1M
–2:VdB (OUT)
VdB (OUT)
–1:VdB (OUT)
Access to the feedback network is provided at Pin 5 (FDBK).
The user may program the gain of the AD603’s output amplifier
using this pin, as shown in Figure 2. There are three modes: in
the default mode, FDBK is unconnected, providing the range
+9 dB/+51 dB; when V
OUT
and FDBK are shorted, the gain is
lowered to –11 dB/+31 dB; when an external resistor is placed
between V
OUT
and FDBK any intermediate gain can be achieved,
for example, –1 dB/+41 dB. Figure 3 shows the nominal maxi-
mum gain versus external resistor for this mode.
Figure 3. Gain vs. R
EXT
, Showing Worst-Case Limits
Assuming Internal Resistors Have a Maximum Tolerance
of 20%
REV. C
–5–
AD [ ANALOG DEVICES ]
