AD574A
CIRCUIT OPERATION
DRIVING THE AD574 ANALOG INPUT
The AD574A is a complete 12-bit A/D converter which requires
no external components to provide the complete successive-
approximation analog-to-digital conversion function. A block
diagram of the AD574A is shown in Figure 1.
+5V SUPPLY
V
LOGIC
DATA MODE SELECT
12/8
CHIP SELECT
CS
BYTE ADDRESS/
SHORT CYCLE
A
O
READ/CONVERT
R/C
CHIP ENABLE
CE
+12/+15V SUPPLY
V
CC
+10V REFERENCE
REF OUT
ANALOG COMMON
AC
REFERENCE INPUT
REF IN
-12/-15V SUPPLY
V
EE
BIPOLAR OFFSET
BIP OFF
10V SPAN INPUT
10V
IN
1
2
3
4
5
6
7
COMP 12
8
9
10
19.95k
11
12
13
5k
9.95k
5k
DAC N
V
EE
10V
REF
I
DAC
I
DAC
=
4 x N x I
REF
I
REF
8k
CLOCK
3k
SAR
12
CONTROL
3
S
T
A
T
E
O
U
T
P
U
T
B
U
F
F
E
R
S
MSB
28
N
I
B
B
L
E
A
N
I
B
B
L
E
B
N
I
B
B
L
E
C
LSB
STATUS
STS
DB11
27
MSB
26 DB10
25 DB9
24 DB8
23 DB7
22 DB6
21 DB5
20 DB4
DIGITAL
DATA
OUTPUTS
The internal circuitry of the AD574 dictates that its analog
input be driven by a low source impedance. Voltage changes at
the current summing node of the internal comparator result in
abrupt modulations of the current at the analog input. For accu-
rate 12-bit conversions the driving source must be capable of
holding a constant output voltage under these dynamically
changing load conditions.
FEEDBACK TO AMPLIFIER
V+
AD574A
CURRENT
LIMITING
RESISTORS
R
IN
I
IN
IS MODULATED BY
I
IN
i
TEST
i
DIFF
CURRENT
OUTPUT
DAC
19 DB3
18 DB2
V–
CHANGES IN TEST CURRENT.
AMPLIFIER PULSE LOAD
RESPONSE LIMITED BY
OPEN LOOP OUTPUT IMPEDANCE.
COMPARATOR
17 DB1
DB0
16 LSB
15
DIGITAL COMMON
DC
ANALOG COMMON
SAR
20V SPAN INPUT 14
20V
IN
AD574A
12
Figure 2. Op Amp – AD574A Interface
Figure 1. Block Diagram of AD574A 12-Bit A-to-D Converter
When the control section is commanded to initiate a conversion
(as described later), it enables the clock and resets the successive-
approximation register (SAR) to all zeros. Once a conversion
cycle has begun, it cannot be stopped or restarted and data is
not available from the output buffers. The SAR, timed by the
clock, will sequence through the conversion cycle and return an
end-of-convert flag to the control section. The control section
will then disable the clock, bring the output status flag low, and
enable control functions to allow data read functions by external
command.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most significant bit
(MSB) to least significant bit (LSB) to provide an output cur-
rent which accurately balances the input signal current through
the 5 kΩ (or 10 kΩ) input resistor. The comparator determines
whether the addition of each successively-weighted bit current
causes the DAC current sum to be greater or less than the input
current; if the sum is less, the bit is left on; if more, the bit is
turned off. After testing all the bits, the SAR contains a 12-bit
binary code which accurately represents the input signal to
within
±
1/2 LSB.
The temperature-compensated buried Zener reference provides
the primary voltage reference to the DAC and guarantees excel-
lent stability with both time and temperature. The reference is
trimmed to 10.00 volts
±
0.2%; it can supply up to 1.5 mA to an
external load in addition to the requirements of the reference in-
put resistor (0.5 mA) and bipolar offset resistor (1 mA) when
the AD574A is powered from
±
15 V supplies. If the AD574A is
used with
±
12 V supplies, or if external current must be sup-
plied over the full temperature range, an external buffer ampli-
fier is recommended. Any external load on the AD574A
reference must remain constant during conversion. The
thin-film application resistors are trimmed to match the
full-scale output current of the DAC. There are two 5 kΩ input
scaling resistors to allow either a 10 volt or 20 volt span. The
10 kΩ bipolar offset resistor is grounded for unipolar operation
and connected to the 10 volt reference for bipolar operation.
The output impedance of an op amp has an open-loop value
which, in a closed loop, is divided by the loop gain available at
the frequency of interest. The amplifier should have acceptable
loop gain at 500 kHz for use with the AD574A. To check
whether the output properties of a signal source are suitable,
monitor the AD574’s input with an oscilloscope while a conver-
sion is in progress. Each of the 12 disturbances should subside
in 1
µs
or less.
For applications involving the use of a sample-and-hold ampli-
fier, the AD585 is recommended. The AD711 or AD544 op
amps are recommended for dc applications.
SAMPLE-AND-HOLD AMPLIFIERS
Although the conversion time of the AD574A is a maximum of
35
µs,
to achieve accurate 12-bit conversions of frequencies
greater than a few Hz requires the use of a sample-and-hold
amplifier (SHA). If the voltage of the analog input signal driving
the AD574A changes by more than 1/2 LSB over the time
interval needed to make a conversion, then the input requires a
SHA.
The AD585 is a high linearity SHA capable of directly driving
the analog input of the AD574A. The AD585’s fast acquisition
time, low aperture and low aperture jitter are ideally suited for
high-speed data acquisition systems. Consider the AD574A
converter with a 35
µs
conversion time and an input signal of
10 V p-p: the maximum frequency which may be applied to
achieve rated accuracy is 1.5 Hz. However, with the addition of
an AD585, as shown in Figure 3, the maximum frequency
increases to 26 kHz.
The AD585’s low output impedance, fast-loop response, and
low droop maintain 12-bits of accuracy under the changing load
conditions that occur during a conversion, making it suitable for
use in high accuracy conversion systems. Many other SHAs
cannot achieve 12-bits of accuracy and can thus compromise a
system. The AD585 is recommended for AD574A applications
requiring a sample and hold.
An alternate approach is to use the AD1674, which combines
the ADC and SHA on one chip, with a total throughput time of
10
µs.
–6–
REV. B
AD [ ANALOG DEVICES ]
