AD574A
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 for a 10 V range). Trim R2 to
give the last transition (1111 1111 1110 to 1111 1111 1111).
BIPOLAR OPERATION
STATUS
R/C
CE
CS
CONVERT
START CONVERT
The connections for bipolar ranges are shown in Figure 5.
Again, as for the unipolar ranges, if the offset and gain specifica-
tions are sufficient, one or both of the trimmers shown can be
replaced by a 50
Ω ±
1% fixed resistor. Bipolar calibration is
similar to unipolar calibration. First, a signal 1/2 LSB above
negative full scale (–4.9988 V for the
±
5 V range) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963 V the
±
5 V range) is applied and R2 trimmed to
give the last transition (1111 11111110 to 1111 1111 1111).
2 12/8
3 CS
4 A
O
5 R/C
6 CE
R2
100Ω
GAIN
STS 28
27
HIGH
BIT 24
MIDDLE 23
BITS 20
LOW IF CONVERSION
IN PROGRESS
A0
READ
VALUE OF A0
AT LAST CONVERT
COMMAND
EOC8
EOC12
FROM
NOTE 1
12/8
(NOTE 2)
NIBBLE A, B,
ENABLE
NIBBLE C
ENABLE
NIBBLE B = O
ENABLE
TO OUTPUT
BUFFERS
NOTE 1: WHEN START CONVERT GOES LOW, THE EOC (END OF CONVERSION) SIGNALS GO LOW.
EOC8 RETURNS HIGH AFTER AN 8-BIT CONVERSION CYCLE IS COMPLETE, AND EOC12
RETURNS HIGH WHEN ALL 12-BITS HAVE BEEN CONVERTED. THE EOC SIGNALS PREVENT
DATA FROM BEING READ DURING CONVERSIONS.
NOTE 2: 12/8 IS NOT A TTL-COMPATABLE INPUT AND SHOULD ALWAYS BE WIRED DIRECTLY TO
V
LOGIC
OR DIGITAL COMMON.
AD574A
10 REF IN
8 REF OUT
LOW 19
BITS 16
Figure 6. AD574A Control Logic
OFFSET
5V
ANALOG
INPUTS
10V
12 BIP OFF
R1
100Ω
+5V
13 10V
IN
+15V
14 20V
IN
9 ANA COM
7
–15V 11
DIG COM 15
1
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
Table I. AD574A Truth Table
CE
CS
R/C 12/8
Figure 5. Bipolar Input Connections
CONTROL LOGIC
A
O
X
X
0
1
Operation
None
None
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
Enable 12-Bit Parallel Output
Enable 8 Most Significant Bits
Enable 4 LSBs + 4 Trailing Zeroes
0
X
1
1
1
1
1
X
1
0
0
0
0
0
X
X
0
0
1
1
1
X
X
X
X
The AD574A contains on-chip logic to provide conversion ini-
tiation and data read operations from signals commonly avail-
able in microprocessor systems. Figure 6 shows the internal
logic circuitry of the AD574A.
The control signals CE,
CS,
and R/C control the operation of
the converter. The state of R/C when CE and
CS
are both
asserted determines whether a data read (R/C = 1) or a convert
(R/C = 0) is in progress. The register control inputs A
O
and
12/8 control conversion length and data format. The A
O
line is
usually tied to the least significant bit of the address bus. If a
conversion is started with A
O
low, a full 12-bit conversion cycle
is initiated. If A
O
is high during a convert start, a shorter 8-bit
conversion cycle results. During data read operations, A
O
deter-
mines whether the three-state buffers containing the 8 MSBs of
the conversion result (A
O
= 0) or the 4 LSBs (A
O
= 1) are
enabled. The 12/8 pin determines whether the output data is
to be organized as two 8-bit words (12/8 tied to DIGITAL
COMMON) or a single 12-bit word (12/8 tied to V
LOGIC
). The
12/8 pin is not TTL-compatible and must be hard-wired to
either V
LOGIC
or DIGITAL COMMON. In the 8-bit mode, the
byte addressed when A
O
is high contains the 4 LSBs from the
conversion followed by four trailing zeroes. This organization
allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
It is not recommended that A
O
change state during a data read
operation. Asymmetrical enable and disable times of the
three-state buffers could cause internal bus contention resulting
in potential damage to the AD574A.
Pin 1 X
Pin 15 0
Pin 15 1
TIMING
The AD574A is easily interfaced to a wide variety of micropro-
cessors and other digital systems. The following discussion of
the timing requirements of the AD574A control signals should
provide the system designer with useful insight into the opera-
tion of the device.
Table II. Convert Start Timing—Full Control Mode
Symbol
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
t
C
Parameter
STS Delay from CE
CE Pulse Width
CS
to CE Setup
CS
Low During CE High
R/C to CE Setup
R/C Low During CE High
A
O
to CE Setup
A
O
Valid During CE High
Conversion Time
8-Bit Cycle
12-Bit Cycle
Min
300
300
200
250
200
0
300
10
15
24
35
Typ Max
400
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
–8–
REV. B
AD [ ANALOG DEVICES ]
