AD558
OUTPUT
AMP
16
15
14
13
V
OUT
–V
V
OUT
SENSE
V
OUT
SELECT
AGND
0.5mA
ADDRESS BUS
16
16
ADDRESS SELECT
PULSE LOGIC
8080A
MEMW
CS
CE
AD558
V
OUT
DB0–DB7
b. 0 V to 10 V Output Range
Figure 11. Offset Connection Diagrams
INTERFACING THE AD558 TO MICROPROCESSOR
DATA BUSES
8
8
DATA BUS
MEMW
→
CE
DECODED ADDRESS SELECT PULSE
→
CS
The AD558 is configured to act like a “write only” location in
memory that may be made to coincide with a read only memory
location or with a RAM location. The latter case allows data
previously written into the DAC to be read back later via the
RAM. Address decoding is partially complete for either ROM
or RAM. Figure 12 shows interfaces for three popular micropro-
cessor systems.
ADDRESS BUS
16
6800
VMA
CS
V
OUT
b. 8080A/AD558 Interface
8
ADDRESS BUS
MA 0 – 7
TPA
1802
MWR
8
ADDRESS
LATCH
&
DECODE
CS
AD558
CE
DB0–DB7
V
OUT
16
ADDRESS
DECODER
8
DATA BUS
8
φ
2
R/W
8
CE
AD558
DB0–DB7
CDP 1802: MWR
→
CE
DECODED ADDRESS SELECT PULSE
→
CS
c. 1802/AD558 Interface
Figure 12. Interfacing the AD558 to Microprocessors
8
DATA BUS
R/W
→
CE
GATED DECODED ADDRESS
→
CS
a. 6800/AD558 Interface
Performance
(typical @ +25 C, V
LSB
1.75
1.50
1.25
1.00
0.75
0.50
FULL
0
SCALE
–0.25
ERROR
–0.50
–0.75
–1.00
–55
–25
0.25
CC
+5 V to +15 V unless otherwise noted)
ALL AD558
AD558S, T
ZERO
ERROR
LSB
1/2
1/4
ALL AD558
AD558S, T
0
–55
–1/4
1LSB = 0.39% OF FULL SCALE
–25
0
+25
+50
+75
+100
+125
oC
–1/2
0
+25
+50
+75 +100
1LSB = 0.39% OF FULL SCALE
+125
oC
Figure 13. Full-Scale Accuracy vs. Temperature
Performance of AD558
Figure 14. Zero Drift vs. Temperature Performance
of AD558
REV. A
–7–
AD [ ANALOG DEVICES ]
